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Oscillator jitter transient simulatin in spectre

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mangk

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Oscillator jitter transient simulation in spectre (Jitter varies each time)

Hi,

I am currently designing an ring oscillator of 100-200 MHz frequency, and have to measure the absolute jitter using transient simulation.

The schematic consists of a 5 stage ring oscillator and an ideal voltage source of 1 V to power the osc.

A jitter was measured using abs_jitter function, which is a built-in function in the calculator of ADE X environment.

Since the function compares and measures a switching timing difference between the osc and an ideal clock, if any noise source is not inserted in the circuit, resulting jitter value should be same, if simulated well.

However, whenever I simulate the circuit, changing some settings like simulation time or an additional circuit, resulting jitter varies drastically even though the schematic is not changed.

For example,

(Simulation 1-1) The peak to peak of the jitter (jpp) was calculated as 0.042 zs (zs: 10^-21 second)
(Simulation 1-2) However, jpp becames 400 zs when I changed simulation time to 50 us from 10 us.
(Simulation 1-3) Also, when I changed simulation time to 500 us, jpp varies to 26 as (as: 10^-18 second)
(Simulation 2) When I inserted dummy transistors in the schematic, jpp was measured 43 zs (Simulation time: 10 us)
(Simulation 3-1) When I inserted a dummy sine wave in the schematic, jpp becames to 120 zs (Amplitude: 100mV, Freq: 900 MHz). In this case, the osc frequency is increased by 60 kHz.
(Simulation 3-2) When I changed the the dummy signal frequency to 9 GHz, jpp becames to 1 fs. Also, the osc frequency was increased by 80 kHz.

Since the theoretical jitter of ideal osc is 0 s, and also since it might be difficult to output '0' by subtracting two values, the result of as to zs order might be reasonable value.

However, I think the flucturation of jpp should be checked.

Can anyone explain the situation? Why it happend and how to solve?

Help me please, thank you in advance!
 
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Measuring is fine, but first you have to induce the jitter.

A determinstic jitter may reveal itself if your schematic
has enough realism (couplings and edge alignments).

A random jitter requires a random source of perturbation
(realistically, some plurality of them and all realistic as
far as their "victim's" sensitivity and the character of
the random noise source (impedance, frequency profile).

It's unlikely you will attain realism without a few passes
around a "cut and try, then measure" human-in-the-loop
exercise. Easier to back-fit a simulation to a known bench
response, than to predict from first principles.
 

Thank you for your advice, but unfortunately, I don't have a known test bench.

The purpose of this simulation is to set a reliable jitter test environment.

Just 'conservative' setting of errprest seems to not enough, I think.

Frequency shifting, by an unused dummy signal (Simulation 3-1, 3-2), is also significant, since it must be a fake result and it can lead to misinterpretation when analyzing a circuit, as the schematic get larger and more sophisticated.

Can you give me a clue to get a reliable result..?

Thank you for helping me
 

That is the numerical garbage from the simulator that you are seeing and should not be considered as the jitter. You can tighten simulator reltol and abstol and this should reduce but will never go away. Another thing to note is that ADE-XL interpolates between simulated points which results in some some numerical inaccuracies of it own. zs is really too small.

If you want to see jitter, run transient noise analysis or alternatively run PSS + PNOISE analysis.
 

Transient Analysis does not measure Jitter..How it's gonna do that ?? Even Transient Periods are not same at t=0 and t=any and vary by time.
Jitter is related to Phase Noise in Frequency Domain.If you do PSS+PNOISE, you can see Jitter while measuring..
 

vivekroy,

Yes I think so too.

However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on) the jitter was simulated to tens of pico seconds.

It should be much smaller than the order, since the circuit is still in ideal condition and also the required design specification is around 10 ps.

ps jitter by simulation inaccuracy is not acceptable.

Would it be okay if I get a much smaller number through tightening reltol and abstol.

Thank you for your information.

- - - Updated - - -

BigBoss,

The absolute jitter can be measured in time domain by comparing ideal clock signal, since it measures a switching time difference of two signal on time axis.

I know that the phase noise is just a different interpretation of the same phenomenon.

Can you explain more detail please..? and I would like to ask you whether PSS+PNOISE can measure the absolute jitter.

Thank you for your suggestion
 
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However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on)
the jitter was simulated to tens of pico seconds.
No.
It is simulation's artifact noises not jitter.
As far as you use conventional Transient Analysis, you can never get jitter.

Use Transient Noise Analysis instead of conventional Transient Analysis.

PSS+PNOISE can measure the absolute jitter.
Yes, use PSS+TDnoise.
 

vivekroy,

Yes I think so too.

However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on) the jitter was simulated to tens of pico seconds.

It should be much smaller than the order, since the circuit is still in ideal condition and also the required design specification is around 10 ps.

ps jitter by simulation inaccuracy is not acceptable.

Would it be okay if I get a much smaller number through tightening reltol and abstol.

Thank you for your information.

As pointed out by others as well, its not jitter and lets not refer to it as jitter anymore to avoid confusion. You should also specify values for maxstep for further reducing simulator inaccuracies.
 

vivekroy,

OK. then, is there an useful way to distinguish 'the real jitter' and 'simulation inaccuracy' if simulation is conducted in noisy condition?

To me, the error by simulation inaccuracy fluctuates quite dramatically and unpredictably, making simulation results unreliable.

How can I certain that simulation is conducted well?

Any advice would help me a lot. Thank you.

- - - Updated - - -

pancho_hideboo

Thank you for sharing!

I have another question.

In simulation 3-1, 3-2 of the first post, the oscillator frequency had been changed by a dummy signal.

How do you think about that?

It should also be solved, since I will use the signal for a specific period in later simulation.

Would it be possible to fix the problem by adjusting simulation parameters(maxstep, reltol, abstol...)?
 

then, is there an useful way to distinguish 'the real jitter' and 'simulation inaccuracy' if simulation is conducted in noisy condition?
It seems you still think numerical error as noise.
Conventional Transient Analysis never gives any device noise.

Do you surely use Transient Noise Analysis ?

In simulation 3-1, 3-2 of the first post, the oscillator frequency had been changed by a dummy signal.
How do you think about that?
It should also be solved, since I will use the signal for a specific period in later simulation.
Would it be possible to fix the problem by adjusting simulation parameters(maxstep, reltol, abstol...)?
Tighten “relref” and “maxstep”.
However “noisefmax” is most important in Transient Noise Analysis.

I recommend you to use time domain noise analysis than transient noise analysis.

Former is small signal Noise Analysis, latter is large signal noise analysis.
 
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pancho_hideboo,

What I meant was a transient simulation of osc whose output buffer is powered by a non-ideal power source (1 V + "noisy power").

The noise power can be 'an 1 tone sine wave' or 'an irregular PWL voltage source, modeling a complex external load'.

In my view, since the power supply is not ideal (making buffer's speed irregular) the osc's output would deviate from its ideal position.... which means jitter. Am I right?

Thus, I thought that knowing an error by a simulation inaccuracy is important, since it always would be included in the simulation (no transient noise option to exclude RJ)

However, although transient noise is applied, is not it important to know the simulation error?

Umm.... My ultimate goal of this simulation is to measure DJ which is caused by an irregular noise of VDD of osc buffer.

Could you give me an advice please ?

Thank you.
 
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You can not understand Rj and DJ.

Show me netlist portion regarding signal sources, analysis statements and option statements.

Use PSS/TDnoise.
 

What I meant was a transient simulation of osc whose output buffer is powered by a non-ideal power source (1 V + "noisy power").

You are contradicting your original question. In the original post, you mentioned

The schematic consists of a 5 stage ring oscillator and an ideal voltage source of 1 V to power the osc.

I am very confused now about your question.

How have you selected the frequency of the supply noise tone? Accumulated jitter would be more sensitive to low frequency supply variation but you need to simulate for a longer period to see its full impact. Period jitter would be more sensitive to high frequency noise but the you need to properly align the edges of your noise waveform with that of the oscillator. Without this information atleast I cannot guide you in telling what might be wrong in your simulation.

Alternatively use a PSS analysis to study the impact of upconversion and downconversion of noise.
 

Thank you for your attention.

For some reason, since I cannot upload my script to the Internet, I will describe my goal more clearly.

* Purpose: Measuring a jitter by a power supply noise, NOT by an intrinsic device noise

* Schematic: 5 stage ring oscillator (from clean 1 V) + load buffer (from noisy 1 V, which is modeled by a pwl source)

* Transient analysis option: errpreset=conservative, transient noise: disabled (to measure a jitter by power noise)

So, I thought that it will be necessary to set an environment (schematic+simulation option) that can reliably measure a jitter, which might output 0 s jitter.

If the environment is prepared, the only action required might just changing a ideal power to noisy one, I thought.

However, since that plan had not been conducted well due to a uninterpretable result, I changed the schematic as described in the first post and many problem had been found explained above.

Is there a problem to my plan?

Hope this conveys my intention well. I am not good at English...

Thank you
 

Please refer to the post to pancho_hideboo, that will be uploaded soon.

I think my explanation was insufficient.

Thank you.
 

Anyway, as you have proposed, I will study PSS simulation after tomorrow.

I am greatly look forward to learning new simulation method.. which might be very informative.
 

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