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    Zero threshold MOSFET design

    Hello,

    I'm a complete beginner to fabrication processes and IC design. I'm an amateur PCB designer and aspiring analog circuit designer. However, this summer I'm working on a research project that's delving into device physics and fabrication a little bit, and I'm very lost.

    I've designed a circuit that operates well using an ALD110900 zero threshold MOSFET. However, I need to make the circuit very small if I want it to work for my intended purpose, and the ALD MOSFET is huge (relatively) for my application. I'd also like to have complete control over design parameters, so I figured I should learn how to design a zero-threshold MOSFET, but the learning process has been tough.

    I've found this paper that mentions 0.13 um IBM CMOS MOSFETS.
    http://sbmicro.org.br/sforum-eventos/sforum2012/028.pdf

    I have also found this post with fairly detailed information on zero threshold MOSFETS.
    https://www.edaboard.com/showthread....eshold-MOSFETs

    Both resources have been extremely useful, but I'd like to learn more. Specifically I want to ask some questions that might be common knowledge to people in the field.

    I want some direction from you guys for good learning material so I don't go down a fruitless path. What is the industry standard modelling software for these MOSFETS? Can I have one of these prototyped in a fabrication house? What is a good learning resource for a total beginner for both modelling software and fabrication education? Is there any information that the experts would like to share on zero threshold MOSFETS? What is the industry standard 'Altium' or 'OrCAD' of the MOS design world?

    In case it affects your answer, a couple of details about the circuit: it is an oscillator that works on a supply voltage of 0.3 volts. I cannot use inductors because they are large, and I'd eventually like to get it all on one CMOS process. I also cannot use a charge pump because the circuit is for remote sensing, so no wires can attach and no inductors can be used for RF coupling the clock signal in.

    Any help is greatly appreciated!

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  2. #2
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    Re: Zero threshold MOSFET design

    If you're talking about the "design" of a transistor species in
    a foundry flow, that's really more process design than device.
    The norm is that "zero-VT" (aka "native") devices share the
    same groundrules (X-Y layout) and either omit or adjust the
    threshold implant for the special case.

    RFIC technologies commonly offer a native NMOS, meant to
    be run hot for RF amplifier applications. Also handy for mixers
    and possibly RF switches (some folks like zero-VT with split
    control rails, for best FET Ron/Coff; some like regular-VT and
    single positive supply, for simplicity).

    Odds are that nobody will play with you, if you come asking
    for a special recipe (or, you will be presented the tab for a
    "customer owned tooling" process development.

    Good news is, many many "pure play" foundries offer flows
    with zero-VT FETs on the menu, and multiproject lots that
    give you some quantity of dice for a couple tens of $K.

    Modeling of process and device would use something like
    PISCES / SUPREM (back in the day), Silvaco TCAD tools
    perhaps, this is not IC circuit or PCB design tools territory.
    I'd forget about trying to architect the FET and its wafer
    fabrication flow, and just do some "catalog shopping" for
    convenient, affordable multiproject fab runs that have
    the device you want.

    TowerJazz CA18 family is one such. Probably a few flows at
    ONSemi. Stuff that runs in Pocatello would probably offer
    you a pretty friendly multiproject pricing (relative to the cost
    of a bespoke mask set and wafer boat, at least). TowerJazz
    has a few flavors of SOI (thin / FD, thick / PD) too, if you are
    looking for lowest power for an RF application these could
    help you out. CS13, CS18 are FDSOI. CA18 has the thick film
    SOI family members.


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  3. #3
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    Re: Zero threshold MOSFET design

    Thank you very much! Catalog shopping sounds like a good fit for my application. Those facilities you mentioned by name are extremely helpful for a beginner like myself, because there is no catch all electronics shop like a 'digikey of the fabrication world'.

    The price is somewhat concerning for a research lab, but if we receive the right funding, it's definitely on the table. It's good to at least know where I can find this technology, what it costs, and what is possible with it. This can demonstrate proof of concept and scalability.

    Oddly enough, I don't need super advanced RF performance or a low Rds,on. I'm working around 50 kHz. The MOSFET resistance must be close to the drain resistance for oscillations to occur with my specific circuit, and we don't want to draw a lot of current. I've actually found the higher resistance and outdated ALD110900 to be better suited for my application than the lower resistance and newer ALD212900.

    Just curious, I'm beginning to take coursework in IC fabrication next year. Are these kinds of native transistors capable of being fabricated by a capable/educated pHd student? The course syllabus lists two main projects: fabrication of a diode and fabrication of a MOSFET. I'm sure the devices we are fabricating will be a standard PN diode and NMOS, but it would be great if I could learn to create a native transistor down the road.



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  4. #4
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    Re: Zero threshold MOSFET design

    One possible option could be "FET-quad mixers" which I have
    seen made of zero-VT devices, 4 in a bridge. But these tend
    to be made for 50-ohm systems and low-ish insertion loss at
    that impedance, which seems contrary to what you want.

    Since native transistors are just permutation, substitution,
    omission of key implants I'm sure you could make them in
    any CMOS flow (provided you have a fortunate starting
    material resistivity, or are willing to counter-dope the body
    or the gate). Equipment set is surely capable. Whether you
    will be allowed (let alone encouraged) to touch the knobs,
    will have to be revealed.

    In a university setting, you might look to internal collaboration
    (maybe some other person or department is already signed up
    for a multiproject run on a RF process that suits, and wouldn't
    miss a fractional square millimeter of reticle area for you to put
    a couple of pad-strips and attach some circuit chunks).


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  5. #5
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    Re: Zero threshold MOSFET design

    Alright. I will look into quad mixers. Even if they do not specifically suit my resistance criteria, it could lead to other options, so thank you for the suggestion.

    I'm working on getting in touch with towerjazz and ON. It looks like they should have a good selection, but we'll see what their support agents say. Thankfully my MOSFET criteria aren't too strict, but it would be nice to have access to some of their models to see if it would work for my needs. Unfortunately it seems that native transistors do not play kindly with SPICE simulations, though.

    That's a great idea. Hopefully someone in the RF department has some connections.

    Thanks again for your help.



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