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    Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi everyone,

    I'm an analog designer performing my first mixed-signal chip now and I have some confusion about input and output delay constraints.
    Basically I have a 5-bit thermometer decoder now written in RTL which takes it's input data from the bondpads of the chip and the output of the thermometer decoder drive switches in an analog block.
    Eventually the parallel inputs will be driven using a ParBERT which has delay control. So I am unsure of how I should set my input delay constraint?
    Also the output of my decoder drives switches in an analog block, how should I set this output delay constraint as this isn't "sampled" by a clock no more of a future module?

    Furthermore, I was wondering if inputs directly connected to a bondpad need some additional attention? I guess putting e.g. some inverters to restore the edges of the signal, but won't the synthesis tool optimize them out?
    Is there any best practice advice for this?

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    Re: Input & output delay in mixed signal chip - RTL Signal Integrity

    1) regarding input delay constraints: these are used when the inputs are clocked, so you specify a delay with respect to the clock edge. it sounds to me that you have async inputs instead. you shouldn't use input delay constraints. the tools will take care of all the buffering necessary to make the signal arrive without deteriorating. this is trivial.

    2) same thing for output delays, it is always with respect to a clock edge. this time you do have a clock, the clock that is internal to the digital part. you specify how much time the logic has to resolve between the last flop on your digital block and the input pin of the analog block. the tools can do this pretty well too, as long as the analog block is well characterized (as a load).
    Really, I am not Sam.



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    Re: Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi ~Sam,

    Thank you for your reply. On point 1 the input constraints, I'm not sure I understand how they are asynchronous. The inputs are 5 bits parallel. The modules I will be using are in the attachment (I will use the 7Gb/s generator module) so these generate this data on the rythm of the CLK which will also drive the chip. But from the datasheet it seems that these generators have great capabilities in setting delays. So inputs will definitely be clocked, but the delays can be adjusted. That is why I am unsure about what the input delay constraint is, as this is the time needed for the signal to travel from the generator -> SMA cables -> PCB -> bondwires up to the first flop. If path length's are somewhat equal I guess they will arrive practically at the same moment. But then again, I can delay e.g. the clock as I need to make sure the setup time of the first flop is respected if this makes sense? So I think I can safely set the minimal input delay constraint zero (meaning clock & data arrive at the same moment) and I can set the the maximum input delay to a value of how much I would like to delay the clock, maybe 1/2 of a period?

    For the output I am wondering if there are special constraints to keep the skew between the digital outputs minimal ? (as they will toggle my transistors preferably at exactly the same time to limit glitches) I can further take care the path lengths in the routing between the digital & analog block, but the skew on the digital should already be minimal for this to have any effect. Any ideas for this?



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    Re: Input & output delay in mixed signal chip - RTL Signal Integrity

    From your first post there was no way I could know the inputs were synchronous. That is probably for the best, makes things simpler.
    However, "this is the time needed for the signal to travel from the generator -> SMA cables -> PCB -> bondwires up to the first flop" <- this is wrong. the input delay constraint is with respect to the clock. It's a relative delay, not absolute. It's best to be conservative here and give the tools some margin.

    As to the outputs, you can constrain all of them with a tight timing and the tools will do their best to make them meet the timing. Zero skew is impossible to achieve, but you can get them pretty close to each other and pass the uncertainty ahead for the next chip/board/equipment or whatever is connected to the outputs.
    Really, I am not Sam.



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