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    I/O banks in an FPGA. Is it important for routing?

    Hello!

    When I'm routing the outputs of an FPGA (pin assignment), there is a pin map in Quartus II.
    There are several "IO banks". My question is simple: if I route a bus (for example 16 bit) to
    outside world, is it better to choose these 16 bits from the same bank or simply it doesn't
    matter?

    Thanks,

    Pastel

    By the way, to the moderators: when posting I had the following message:
    The title that you have entered is too short (19 characters). Please change it to minimum 20 characters long.
    The title was "IO banks in an FPGA" which is indeed 19 characters. I add / between I and O, but the same
    message still displays. I added "I/O banks in an FPGA. Is it important for routing?" to be sure I'm way
    over 20, but the same message is still displayed... I'm going to try the 2nd "submit new thread" button
    at the bottom of the page. Let's see...

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    Re: I/O banks in an FPGA. Is it important for routing?

    It shouldn’t matter as long as the voltages and IO standard are correct.



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    Re: I/O banks in an FPGA. Is it important for routing?

    It can affect the pcb layout. It also makes higher performance busses more difficult. Beyond any specialized resources that are local to a io-bank, it also can lead to timing errors. The tools like placing circuits mostly near related circuits. The tools also have options to automatically place the last register stage in the io registers. When this happens, the circuit can end up with difficult routes just due to high routing delays to the IO.

    (perhaps the weirdest case I've seen was an engineer that decided to do some simple logic, register it, and send it to a pin connected to a LED. The tools recognized the logic as a copy of some other register's logic and decided to combine them into one register -- the io register -- located on the other side of the FPGA.)



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    Re: I/O banks in an FPGA. Is it important for routing?

    Hello!
    Thanks for your replies.
    That's precisely because of the layout that I was trying to get info. But if there are also timing
    issues, OK, I will route from the same IO bank. And beside this, from the very few FPGAs I have
    checked, an IO bank seems to be grouped in one particular area of the FPGA, so I can try to
    set it close to the connected chip.

    By the way, I'm going to use a MAX10. I have noticed that there are some differential pairs
    named for example DIFF_OUT_T45p and DIFF_OUT_T45n. If I use plain single end signal, can I
    use these separately? For example if I'm routing a data bus, is it a problem to route DATA0
    to DIFF_OUT_T45p and DATA1 to DIFF_OUT_T45n or will the p and n automatically be the
    positive and negative of the same signal?

    Thanks!

    Pastel



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    Re: I/O banks in an FPGA. Is it important for routing?

    It depends on the device; the user’s manual should tell you if you can use the p and n ports individually. Barring that, the mapping tool will certainly tell you by throwing an error. But my guess is it’s probably allowed.



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    Re: I/O banks in an FPGA. Is it important for routing?

    Hi,

    so I can try to set it close to the connected chip.
    That's a good idea in any case.

    If I use plain single end signal, can I use these separately?
    I never have worked with MAX10, thus I don't know the answer.
    But I'm sure you find the answer in the datasheet.

    Klaus
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    Re: I/O banks in an FPGA. Is it important for routing?

    Bank selection definitely matters for high speed signals. In the range of general purpose I/O, including slower µC busses, it's not so important.



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    Re: I/O banks in an FPGA. Is it important for routing?

    In general modern FPGAs and their tools are quite flexible and forgiving in terms of routing.

    Some people have the idea that you should do your FPGA design, let the tool pick the pins and then use those in your board schematic. I think that's outdated and results in schematics and layouts that are a mess.

    On the other hand timing critical parallel busses and clocks (100Mhz+ perhaps) do matter and ideally you should make at least a stub FPGA design with timing constraints ahead of time to verify your pinout selection.

    I failed to do this on a recent design and get a few nasty warnings that clocks can't follow proper dedicated clock paths.



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    Re: I/O banks in an FPGA. Is it important for routing?

    Hello!
    Thanks for your replies.
    I will use data from the same bank for buses.
    Now there is something I don't understand. I looked at the DE0 nano documentation and
    configured the pins accordingly for data[0] to data[15], which corresponds to the 16 bit
    bus I use for analog generation.
    Click image for larger version. 

Name:	PinPlanner.PNG 
Views:	0 
Size:	27.1 KB 
ID:	154264

    Basically it works and the result of sending bits to a R2R ladder are shown in the attachment.
    Now the pin planner shows the bus in the image above. D15 correspond to the pin which is
    selected in blue. This pin is a VREF (white and brown triangle means VRED), but it also works
    when selected as a GPIO. (Otherwise I wouldn't get a sine wave, it would be "folded" by trunks.
    What I observe is a regular sine wave, so does this mean that any non-power pin can be used
    as a GPIO?
    Or an other way to formulate this question: is there any disadvantage in choosing a VREF pin
    as a GPIO, except the fact that I will not be able to use it as a VREF if necessary?

    Thanks,

    Pastel



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    Re: I/O banks in an FPGA. Is it important for routing?

    Hi,

    I looked at the DE0 nano documentation
    You definitely need to read MAX10 documentation.
    Some pins may have dedicated function, some pins may be configured for different functions.

    Klaus
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    Re: I/O banks in an FPGA. Is it important for routing?

    Hi,

    About the Vref pins? Download and read the Max 10 Handbook, especially pages 3-1 and 3-2.

    - - - Updated - - -

    Better still, the DE0-nano has a Cyclone IV FPGA. Read the Cyclone IV Device Handbook. Relevant information are in chapter 6 of the handbook.
    -------------
    --Akanimo.



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    Hints for pin assignment

    Hello!

    I made a few experiments which worked as I wanted, and I'm about to design
    a PCB with an FPGA.
    As for pin assignment, I had already replies about IO banks and understood that
    it's better to use pins of the same bank for a bus output.
    Now inside of one IO bank, is there any drawback in choosing a pin rather than
    the next one? What I would like to do is avoid using vias if not necessary.
    So sometimes it's more convenient to switch 2 pins in the pin assignment list.
    Example, say I have a package with 2 pins A17 and B16 belonging to the same
    IO bank. Is there any drawback in switching them? If I don't I have to switch them
    on the PCB, which will require a via. And if I do, it's convenient.

    Thanks for any hint!

    Pastel



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    Re: Hints for pin assignment

    I merged the two threads according to forum rules. "Ask related questions in one thread".

    The question has been basically answered by asdf44 in post #8. Single ended I/O pins within a bank can be arbitrarily swept, across banks under circumstances.

    Take care that the FPGA component definition in your CAD tool enables swapping of I/O pins and swap the pins as required during routing. Bank swapping will usually performed in the schematic.

    I presume you reviewed pending questions from previous posts in the FPGA hardware manual, as suggested.



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    Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    Post 8 said "In general modern FPGAs and their tools are quite flexible and forgiving in terms of routing.", which doesn't reply
    clearly to my question.
    Now if you say: "Single ended I/O pins within a bank can be arbitrarily swept", then it's indeed what I wanted to know.
    I supposed you meant "swapped".

    So I suppose that this should apply to anything, right? For instance, I want do add a SPI port, so I can link it to any pin, right?

    I have another question. I received a book about verilog, which is very helpful in my case.
    But I need to know something.

    Basically a verilog program has a top level module which I understand as the main program
    This top level module shows a bunch of outputs and inputs in its parameter list.
    So basically if I want to create a blackbox (fpga with n pins routed to the chip's output), then
    do these n pins have to be listed in the module interface?

    Example: let's say that the output of the device I make will be linked to a DAC. This Dac has
    a parallel input (16 bit) and a latch (1 bit). It receives configurations from a SPI port (MOSI,
    MISO, CLK, CS). Will the top level module have an interface like this:

    Code:
    module my_first_dac(dac_data, dac_cs, dac_latch, miso, mosi, clk, spi_cs);
        output reg[15:0] dac_data;
        output reg dac_cs;
        output reg dac_latch;
        output reg miso;
        input mosi;
        input clk;
        input spi_cs;
    As a summary, do all the assigned FPGA pins have to be part of the top level module
    IO list?

    Thanks!

    Pastel



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    Re: Hints for pin assignment

    Hi,

    Just to try and say the little that time permits.

    Verilog and VHDL are hardware description languages and not computer programming languages.

    When you say that Verilog top level module is like main program in computer program, it's kind of incomparable. Unlike computer programming main program and interrupt jumps, the Verilog top level module is like a big box containing other smaller inter-wired boxes inside it, and letting you have access only the wires that you need to have access to. Moreso, it's not like a computer software program that's stored in memory and called upon to do some function. It's uses to describe the hardware behaviour of a system. More like what is used in making a system hardware that a software program can run on.

    I hope this helps.
    Last edited by Akanimo; 15th July 2019 at 11:38.
    -------------
    --Akanimo.



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    Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    I'm aware that this top module is not like a program. So back to my question:
    If I'm doing a hardware (or let's say a hardware equivalent) of a chip that has 28 pins
    (for instance a 16 bit bus, an input SPI (4 bits) an output SPI (4 bits) and 4 extra pins
    stuff1, stuff2, sfuff3 and sfuff4, is it mandatory that my top level verilog object has
    28 pins in its parameter list (i.e. a 16 bit bus, an input SPI (4 bits) an output SPI (4 bits)
    and 4 extra pins stuff1, stuff2, sfuff3 and sfuff4)?

    Or is there a way to "delegate" the definition of external pins to submodules?

    Thanks,

    Pastel



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    Re: Hints for pin assignment

    No, there is no way to delegates the pins of the chip to submodules.

    In VHDL for instance, you just declare your sub-entity (equivalent to submodule in verilog) as component in the top level 'module' and connect its 'ports' to that of the top level 'module'.

    I believe there should be some equivalent way to do this in verilog.

    For the other question, some of the IC pins can be left unassigned. Your top level module must not have 28 I/O bits for a 28 I/O pin IC. It can have any number between 1 and 28.
    -------------
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    Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    In my example, the 28 pins are supposed to be useful. The 16 bit bus is fully used, the2 input and output SPI engines are fully used.
    And let's admint that the extra lines stuff1 ~ stuff 4 are also used.
    In this case, do all these signals _have_to_ be present in the interface list?

    Thanks,

    Pastel



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    Re: Hints for pin assignment

    Yes, if not they won't be available to be assigned to IC pins.
    -------------
    --Akanimo.



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    Re: Hints for pin assignment

    I believe the question has been already answered by Akanimo. All externally connected IO pins, user clock, reset etc. must be present in the top module interface. But not dedicated pins, e.g. power supply, configuration memory interface.



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