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    copper pour in top layer with vcc net

    hello,

    I have come across the question that i design one 4 layer PCB and in which by mistake i have done copper pour in Top layer with VCC net.
    is this create shorting problem in PCB? or any another problem in PCB?
    Please guide me as soon as possible.

    Thanks

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    Re: copper pour in top layer with vcc net

    There are no hard rules about this as long as the pour isn't shorting anything out.
    Beware of things like metal bodied components or heat sinks that lie against the surface but must not touch VCC.

    Brian.
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    Re: copper pour in top layer with vcc net

    Thank u sir for your prompt reply. In this PCB i am facing the issue that my controller get more current. Controller Current consumption is like almost 400mA and as per datasheet controller's consumption is 50mA.
    Is this problem is due to copper pour?

    Thanks



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    Re: copper pour in top layer with vcc net

    We have no idea of the design of your controller or the exact PCB layout but in general, there are no reasons why you can't use any layer for any connection without problems. Inner layers are usually used for power and ground because they provide some shielding between the outer layers, and so that tracks on the outer layers can more easily be utilized for connecting to components. The increased current you see is almost certainly due to some other effect and not the order of layers.

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    Re: copper pour in top layer with vcc net

    yes sir. Actually in PCB Top layer contains signals only but copper pour of top layer is done by VCC net by mistake.

    Thank you



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    Re: copper pour in top layer with vcc net

    i design one 4 layer PCB and in which by mistake i have done copper pour in Top layer with VCC net
    Should we assume that you ran a DRC check on the final completion of the board design so that all the routed connections match the electrical diagram? If the schematic is correct, there is no reason to assume that there is an error in the PCB side, unless obviously if there is some design error in the electrical schematic side.
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    Re: copper pour in top layer with vcc net

    Technically, if you flood with VCC, as far as signals see it the situation is the same as flooding with GND as they should be at the same signal potential. I'm afraid it looks like some other error is to blame. Is anything mounted flush to the board that might be shorting to the flood area?

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    Re: copper pour in top layer with vcc net

    Posting the gerber files might clarify the problem.

    We have insufficient information yet. If the PCB is made with correct component definitions and design rules, no short should ever happen. The PCB tool will automatically isolate components from copper pour.

    But if your processor has e.g. an exposed pad that isn't correctly described in the component definition, anything may happen.

    There are also specific trapdoors of some CAD tools, e.g. if copper pours are not automatically recalculated during the post process.



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