Facing issue of long runtime to find a legal location for cell , in clock opt stage

Searching legal location of lib cell "BUFFD1BWP240H11P57PDLVT" from (90.00300 227.28000), 4513629 attempts failed, current search location (0.57000 21.60000), current displacement 224.28224 um (934.50934 rows height)
Warning: Could not find legal location for cell instance u_alb_srams/i_arccore_arccore0_bist_wrapper_top/arccore_bc_ram_0_inst/U1(BUFFD1BWP240H11P57PDLVT). (LGL-051)
Warning: Detected unusual long runtime to find a legal location of lib cell "BUFFD1BWP240H8P57PDSVT"
-- Searching legal location of lib cell "BUFFD1BWP240H8P57PDSVT" from (89.09100 224.64000), 4450984 attempts failed, current search location (0.57000 24.24000), current displacement 219.08018 um (912.83410 rows height)
Warning: Could not find legal location for cell instance u_alb_srams/i_arccore_arccore0_bist_wrapper_top/arccore_bc_ram_0_inst/U2(BUFFD1BWP240H8P57PDSVT). (LGL-051)


This keep running indefinitely

any idea why this issue,
I tried doing legalize placement before running clock opt
tried putting soft blockage around the place where the tool is trying to place these cells.

but the issue persists.tool : IC Compiler 2

not sure what is going on. I suspect you messed up the flow or that your density is too high.