Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440'

Status
Not open for further replies.

MSAKARIM

Full Member level 3
Joined
Jun 2, 2015
Messages
154
Helped
1
Reputation
2
Reaction score
4
Trophy points
1,298
Activity points
2,528
I'm trying to synthesize a certain design using Vivado 17.4, but the synthesis was terminated and i have failed message.
No errors appear but i have this message
" Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440' "
Note ( Design is synthesized properly using Xillinx ISE )
 

If you are using the Webpack tools Ultrascale parts are not supported for that version of the tools. You need to have a full purchased license.
 
If you are using the Webpack tools Ultrascale parts are not supported for that version of the tools. You need to have a full purchased license.

I used "Vivado HLS 2017.4".
In Xillinx ISE the design is properly synthesized and implemented using " Defense-grade Virtex-6Q", but i cant find this family in vivado i found (Defense-grade Virtex-7Q) but generated "synthesis failed ".
How can i add this family to vivado "Defense-grade Virtex-6Q" or finding a alternative one.
Note ( i have tried all families in Vivado and gives the same message".
 

I don't have time to look up the part support for Vivado right now, but the information is available on Xilinx's website, but I don't believe that 6Q is supported in Vivado. Vivado was designed for 7 series and beyond. Everything prior to 7 series is only supported on ISE.

The synthesis failed message may be due to cores being generated in a different family on a different tool platform. You may have to generate new IP cores in Vivado for V7Q for it to work properly. I vaguely recall being told by the FAE to generate new IP cores when I migrated a design from K6 to K7 years ago
 
I don't have time to look up the part support for Vivado right now, but the information is available on Xilinx's website, but I don't believe that 6Q is supported in Vivado. Vivado was designed for 7 series and beyond. Everything prior to 7 series is only supported on ISE.

The synthesis failed message may be due to cores being generated in a different family on a different tool platform. You may have to generate new IP cores in Vivado for V7Q for it to work properly. I vaguely recall being told by the FAE to generate new IP cores when I migrated a design from K6 to K7 years ago

Still have the same problem.
 

Note ( Design is synthesized properly using Xillinx ISE )
Adding the ads-ee comments from above....
Xilinx ISE is for Series6 and previous versions of FPGAs.
If your target FPGA has changed, so should your Xilinx tools also.

I am pretty much sure Virtex-6Q and the XVCU* will have different Xilinx primitives.
 

Without posting the actual errors there is little we can do to help.
Do you have a full paid licence for vivado or are you just using the web-pack?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top