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Systemverilog type cast or integer division

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parafux

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Hi all,

i am quite new to systemverilog. I normally code in VHDL. Now i have to do some test bench codings in systemverilog.
I want to get the upper 32 bits of a longint variable.

I do this:
Code: 
             pos1_x_0 = pos1_x % (2**32); // lower bits, works
             pos1_x_1 = int'(pos1_x / (2**32)); // upper bits deliver always zero

I try this for a small negative number like
Code: 
             pos1_x = -10

I expect to get -1 for pos1_x_1 but i get 0



Another way for me would be to convert the longint pos1_x to a vector but i dont know how.



hope anyone can help me.

best regards
p.
 

now i found a solution that works properly for me, but i dont know why the approach above does not work

Code: 
pos1_x_1 = int'(pos1_x >> 32)
 

This is because the compiler is smart, and knows how to do signed divisions properly. And you are doing signed divisions in your original attempts.

If you want to manipulate bits, then you should do bit mask and/or bit shift operations, not signed arithmetic operations.

In your second post, you have done a bit-shift operation, hence it worked as required by you.
 

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