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Help in understanding the paper "Understanding Wide-band MOS transistors"

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circuitking

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Hi, I am reading this paper on MOSFET bandwidth https://www.ece.ucsb.edu/Faculty/rodwell/Classes/ece2c/labs/Steininger.pdf.

I have few questions
1. For figure 4, the small signal equivalent was drawn in Figure 5. I don't understand why the dependent current source of M3 is not included in figure 5 and why gm1/wT (Cgs of M1) is included two times (second time at the output).
2. I know that in compared with single stage, gain increases and bandwidth decreases in a multi-stage. But here it was said that "To obtain an amplifier with the highest possible bandwidth, we would like to cascade stages of low gain" and "It is possible to show that there is an optimum stage gain for a cascade of identical amplifiers that maximizes the overall bandwidth". Can someone explain this clearly.
 

Re: Help in understanding the paper "Understanding Wide-band MOS transistors"

Re 2: There is always a technology gain-bandwidth product
which is your ultimate limit, even if you've done your best
with the rest of the circuit optimization.

A lineup that uses (say) one A=100 amplifier in a fmax=100GHz
technology will probably give you a 1GHz BW.

A lineup that uses the same technology, cascaded A=10 stages
(A=100) but each stage having 10GHz BW, will have a A=100,
BW 10GHz (-ish) but a 2-pole rolloff rather than 1-pole. This
could be good or bad, depending on what you wanted to
happen to incoming and locally generated harmonics, but
probably better than 1GHz BW (especially if you wanted 2GHz
passband).
 

Re: Help in understanding the paper "Understanding Wide-band MOS transistors"

In addition to the answer from dick_freebird, cascading multiple stages will have stability issues and you need to use some form of compensation which will lower your BW.
Edit: *can have stability issues
 

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