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  1. #1
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    pins of symbol and layout do not match

    I encountered this problem when I tried to generate layout from schematics automaticaly.

    Click image for larger version. 

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    Click image for larger version. 

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    after doing connctivity > update > binding I got this result
    Please help me to solve the problem.Your help appreciated

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  2. #2
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    Re: pins of symbol and layout do not match

    Why don't you use directly Layout-XL-->Update ?? What is Binding for ?



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  3. #3
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    Re: pins of symbol and layout do not match

    it tells me that the symbol pins (G D S B) don't correspond to those of the layout(p D S)

    *WARNING* (LX-2003): Cannot create instance terminal on layout instance 'M0' because the instance master 'NCSU_Devices_FreePDK45/NMOS_VTL/layout' does not have a corresponding terminal 'B'.
    *WARNING* (LX-2003): Cannot create instance terminal on layout instance 'M0' because the instance master 'NCSU_Devices_FreePDK45/NMOS_VTL/layout' does not have a corresponding terminal 'D'.
    *WARNING* (LX-2003): Cannot create instance terminal on layout instance 'M0' because the instance master 'NCSU_Devices_FreePDK45/NMOS_VTL/layout' does not have a corresponding terminal 'G'.
    *WARNING* (LX-2003): Cannot create instance terminal on layout instance 'M0' because the instance master 'NCSU_Devices_FreePDK45/NMOS_VTL/layout' does not have a corresponding terminal 'S'.

    *WARNING* (BND-2055): The 'permuteRule' property on cellview 'NCSU_Devices_FreePDK45/NMOS_VTL/layout' was ignored because it contains invalid terminal names, '(p D S)'.
    In the 'Simulation Information' tab of the 'Edit CDF' form for the auLvs simulator,
    set the permute rule for the cell using valid terminal names.
    I don't know how to update pins to match them



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  4. #4
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    Re: pins of symbol and layout do not match

    Is that PDK complete ?? It ought to be..Otherwise there is no sense to use it.
    You cannot make them a pair ( schematic and layout views ) if there is not a corresponding.Either there is an installation error ( missing script or skill function etc.) or the version of Virtuoso layout Editor is not compatible.Have you ever checked primitive layout of the transistor ?? You should see that the pins are there..



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    Re: pins of symbol and layout do not match

    conserning the PDK, the TechLib file contains just layouts ,and schematics are in the NCSU_Devices_FreePDK45 folder, this might be the problem, so I copied the schematics to each cell in the TechLib.
    conserning the skill function I get errors in WIC (photo)
    for the primitive layout I think It doesn't show pins ,but schematics show them, here is an example for NMOS_VTL
    Thank you for your time.
    Click image for larger version. 

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