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Understanding the inversion coefficient proposed by EKV

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Alex Liao

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Hi, I am looking at the inversion coefficient/facotr (IC) used by EKV people. Inspired by this IC, D. M. Binkely and D. Foty. applied it to analog sizing applications.

I think IC is a parameter to express the bias status/condition of a MOSFET, so it should be a DC-op parameter, because as mentioned in EKV's book "Charge-based MOS Transistor Modeling" in 2006, "The notion of inversion coefficient is qualitatively equivalent to that of gate voltage overhead."

I have the following basic question:
A. Is IC a DC-op parameters that can be obtained after finishing a SPICE simulation (has to use EKV model?)

B. From the same book, the defition of IC,
* IC=max(if=IF/Ispec, ir=IR/Ispec),
where IF and IR are the Forward-current and Reverse-current to express that the drain current is the superposition of independent and symetrical effects of the source and drain voltages. So does this mean IC is a parameter defined in all working regions? (in both triode region (or linear region) and saturation region, ignore the cut-off region)

B-1. I know given Vds > Vdsat (saturation region), and when Vgs varies, the MOSFET works from weak inversion to moderate inversion and to strong inversion as can be reflected by the IC factor, are the three inverison-regions also clearly defined and discussed in triode region (when Vds < Vdsat or Vds < Vgs - Vth)? Not sure if this question make sense or not, because I did not find any spcific materials accouting for this point. This will lead to my Question-C.

C. I did see in Binkley 2003's TCAD paper, the IC "in saturation" is defined by,
* IC = ID / ( 2nk(W/L)UT^2 ).
Is there an equation that link IC and ID in triode region?

I konw IC in saturation can be helpful for sizing a Opamp, but I am really not sure about the story of IC in triode region, some circuits use triode region MOSFET as a Resistor or load, so it is not only used in digital application as switches, and thus can be important. :cry:

Appreciate for any response for the questions! thanks.
 

Ad A. It is possible and using EKV in simulation is not necessary. However, you need to characterise transistors (simple dc sweep to get gm/Id curve and extractspecific current). The most common problem with IC in simulations with spice models is lack of information about current gain factor. In some process transistors has beta parameter shown in the dc op card, but usually it is calculated from square law formula and obviously is wrong.

Ad B. Yes it is true. The physics phenomena is clear here. The charge density is important.

AD B-1. Yes, EKV (and other charge based models) is continoues in all inversion levels and both triode and penthode modes. However, the borders between inversion levels are only an agreement (this is nothing more than simple convention).

AD C. If you look on the point B you find an answer. The problem is with reverse current, which has to be calculated. Not sure if it is not provided by Jespers in his PhD?
 

Dominik, thanks for sharing your knowledge.
Ad A. It is possible and using EKV in simulation is not necessary. However, you need to characterise transistors.
I guess current gain factor is beta parameter uCox(W/L). This parameter is obtainable from Cadence Spectre simulation, no problem.

AD B-1. Yes, EKV (and other charge based models) is continoues in all inversion levels and both triode and penthode modes.
If EKV is continoues in all inversion levels and is good in triode region, can this IC be directly printed out like the "beta" parameter after a DC-analysis simulation? or is IC just a design paramter those analog sizing paper authors introduced themself but not directly printable from simulation result?

AD C. If you look on the point B you find an answer. The problem is with reverse current, which has to be calculated. Not sure if it is not provided by Jespers in his PhD?
So from your experience, there is no handy equation for estimating IC in triode region, like "IC = ID / ( 2nk(W/L)UT^2 )" used in saturation region?
 

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