Pastel
Member level 3
Hello!
I have searched the net (and also this site) to clarify the difference between wire and reg.
For instance this website:
https://stackoverflow.com/questions...ence-between-reg-and-wire-in-a-verilog-module
But it's still quite unclear to me. I more or less understand reg as a variable like in C, and since I can route this
variable to the output, why should I bother with wires? That's basically my concern right now.
The webpage above says that regs might not be synthesizable. What does it mean?
It can be synthesized to FF -> What does it mean?
Can I consider that a reg is a wire with memory capability?
Can I always make an all-reg program, without wires?
Until now, I have used only regs, but is there a disadvantage of using only regs? Maybe it consumes memory?
If anybody could give me examples of programs I cannot do with regs, it would probably help.
Thanks for any hint.
Pastel
I have searched the net (and also this site) to clarify the difference between wire and reg.
For instance this website:
https://stackoverflow.com/questions...ence-between-reg-and-wire-in-a-verilog-module
But it's still quite unclear to me. I more or less understand reg as a variable like in C, and since I can route this
variable to the output, why should I bother with wires? That's basically my concern right now.
The webpage above says that regs might not be synthesizable. What does it mean?
It can be synthesized to FF -> What does it mean?
Can I consider that a reg is a wire with memory capability?
Can I always make an all-reg program, without wires?
Until now, I have used only regs, but is there a disadvantage of using only regs? Maybe it consumes memory?
If anybody could give me examples of programs I cannot do with regs, it would probably help.
Thanks for any hint.
Pastel