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    Verilog wire vs reg. Which one should I use and when / why?

    Hello!

    I have searched the net (and also this site) to clarify the difference between wire and reg.
    For instance this website:
    https://stackoverflow.com/questions/...verilog-module

    But it's still quite unclear to me. I more or less understand reg as a variable like in C, and since I can route this
    variable to the output, why should I bother with wires? That's basically my concern right now.

    The webpage above says that regs might not be synthesizable. What does it mean?
    It can be synthesized to FF -> What does it mean?

    Can I consider that a reg is a wire with memory capability?

    Can I always make an all-reg program, without wires?
    Until now, I have used only regs, but is there a disadvantage of using only regs? Maybe it consumes memory?

    If anybody could give me examples of programs I cannot do with regs, it would probably help.

    Thanks for any hint.

    Pastel

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    Re: Verilog wire vs reg. Which one should I use and when / why?

    the names are based on how they relate to simulation, which is confusing. It has nothing to do with synthesis. reg is used when assigned in an always block, wire otherwise.

    system verilog added a "logic" type to reduce the confusion.



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    Hello!

    Thanks for your reply.

    It has nothing to do with synthesis so what does the above webpage mean by "regs might not be synthesizable"?
    And also It can be synthetized to FF?

    And is it always possible to make a design without wires, with only regs? I mean, I did as explained in another
    post, so it's possible, but is it always possible in any case?

    Thanks,

    Pastel
    Last edited by Pastel; 4th July 2019 at 10:42.



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    A reg used inside an always block leads to the inference of a flop. You use it when you are defining sequential logic.

    When you are writing RTL for combinatorial logic, something outside the always block, use wire. Think of wire such as simply connecting one electrical point to another.

    Please read a good Verilog book, a real book, to clear fundamentals rather than relying on various web sources.
    FPGA enthusiast!



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    Hello!

    Thanks for your reply. I'm waiting for the books ordered earlier this week. On Verilog, VHDL and System Verilog.
    I just wanted to do some experiments in the meantime...

    Pastel



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    A reg used inside an always block leads to the inference of a flop. You use it when you are defining sequential logic.
    A reg inside an edge sensitive always block.

    When you are writing RTL for combinatorial logic, something outside the always block, use wire. Think of wire such as simply connecting one electrical point to another.
    There are also combinational always blocks. A reg keeping its value across block execution cycles infers a combinational loop respectively a latch.



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    A reg inside an edge sensitive always block.
    Yes I meant that.
    FPGA enthusiast!



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    Quote Originally Posted by Pastel View Post
    Hello!

    Thanks for your reply.

    It has nothing to do with synthesis so what does the above webpage mean by "regs might not be synthesizable"?
    And also It can be synthetized to FF?

    And is it always possible to make a design without wires, with only regs? I mean, I did as explained in another
    post, so it's possible, but is it always possible in any case?

    Thanks,

    Pastel
    Small pieces of code yes (module output ports must be connected to a wire) because the choice is a syntax choice and often not a consequential design choice. Reg's may synthesize to wires or reg's depending on how you actually used them.

    So if it's in a begin/end block -> reg
    If not -> wire

    In general you don't use reg unless there is a reason though there are a couple good reasons:
    1) It's actually a reg assigned in an always @(posedge x) block
    2) You want access to syntax that only applies to reg's, such as if/then/else or case

    If the above doesn't apply leave it a wire because while a reg has ambiguity a wire does not.



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    Pratical guide:

    reg comes with "<=" inside always block
    wires comes with "=" (my hint: outside always blocks, altough "=" is accepted by Verilog inside always blocks)

    Bonus: I prefer to use uses only clocks into always blocks "e.g.: always (posedge CLK)" and let all the combinational logic (without clocks) outside always. For example:

    wire combinational_logic, a, b, c;
    assign combinational_logic = (a==1) ? b+c : b-c;



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    Re: Verilog wire vs reg. Which one should I use and when / why?

    regs might not be synthesizable
    I suspect this might just mean that you could write code in always blocks that the synthesis tool won't synthesize. For example, tools will not synthesize while loops except in very specific cases. a "reg" described by assignments in a while loop might not be possible to represent by any circuit. This is especially clear if the while loop never terminates for some input combination.



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