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[SOLVED] Timing slack showing Unconstrained after synthesis in genus

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Are you sure about the "clk"? I think it is only clk, without the " "
Also I would recommand that you dont call the SDC clock clk as the pin, so you allways know which signal you are working with!

My genus works without the "" but I havent tried with!
 

Yes. That was a sample file that i used. it works with my other programs that has one module. Here i am using structural model and that is what i am not sure about.
 

your circuit has no logic, there is nothing to constrain. if you do report_clocks, it should list the clock in there, even without any logic.
 

@NotSam he wrote that he only uploaded the declaration of hi top module

You load all your verilog files, right? What I remember it is important to input the hirachy bottom up, eg.:
read_hdl -vhdl {FlipFlop.vhd counter.vhd wholeCPU.vhd}

Do you use a script to feed genus? if yes enter each command at its own and read EVERY warning that genus gives you, I am quite sure there is one that helps!
 

Alexxk said:
@NotSam he wrote that he only uploaded the declaration of hi top module

You load all your verilog files, right? What I remember it is important to input the hirachy bottom up, eg.:
read_hdl -vhdl {FlipFlop.vhd counter.vhd wholeCPU.vhd}
Click to expand...

You might be right, but the report_clocks command should still work nonetheless. You can also do report_timing -unconstrained to figure out what is happening.

The file order makes no difference for genus, it can be any order. You just have to name the top module explicitly.
 

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