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    How to use array data in Verilog

    Hi guys!

    First thanks a lot for your replies the other day, it allowed me to progress a little bit in my "after five"
    experiments.
    This time, I made a program for a signal generator. I have designed a board for it, but in the meantime
    I wanted to try, so I wired a R/2R ladder and I'm using a 16 bit output. Here is a picture of what it looks like.
    NB: There are only resistors, and there is no guarantee the the FPGA outputs have a constant current.
    Beside this, I could find out the other day that the channel have a great crosstalk, so I'm not expecting
    too much from this.
    Click image for larger version. 

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    You can see in the attachment below that the result is not that bad considering how it's done. Having
    close to 60 dB from the fundamental to the harmonics is actually quite good for what it is.
    I did this with a 1024-value sine table, and the consumption of components is very moderate.
    I had absolutely no idea at start since I'm a real newbie, of what part of the FPGA it would occupy.
    If the system had report 70% used, I would have said, OK, fine, I have to find a bigger one.

    Click image for larger version. 

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    Now I have one question. Please be tolerant, I am waiting for reference books I ordered, and for the moment
    I'm programming by looking at snippets I find on the net.
    Here is my full progran (except the long sequence of definition which is truncated). I made this file with
    a short php script.

    Code Verilog - [expand]
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    module SineGen(Clk,data_out);
    //declare input and output
        input Clk;
        output [15:0] data_out;
    //declare the sine ROM - 30 registers each 8 bit wide.  
        reg [15:0] sine [0:1023];
    //Internal signals  
        integer i;  
        reg [15:0] data_out; 
    //Initialize the sine rom with samples. 
        initial begin
            i = 0;
            sine[0] = 32768;
            sine[1] = 32969;
            sine[2] = 33170;
            sine[3] = 33371;
            sine[4] = 33572;
    [.....]
     
     
            sine[1020] = 32164;
            sine[1021] = 32365;
            sine[1022] = 32566;
            sine[1023] = 32768;
        end
        //At every positive edge of the clock, output a sine wave sample.
        always@ (posedge(Clk))
        begin
            data_out = sine[i];
            i = i+ 1;
            if(i == 1023)
                i = 0;
        end
    endmodule

    Question: is there an easier way to declare an array?

    I also attach the curve and the spectrum analyzis below.

    Thanks for any hint!

    Pastel
    Last edited by bassa; 2nd July 2019 at 15:26. Reason: add code tag

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