H-Bridge heating without load

Hi
I am testing an H-Bridge circuit and it is heating up without load.
The MOSFET is IPD60R180C7 (600V, 180mOhm Infineon MOSFET). Supply voltage is 250VDC and switching frequency is 100KHz. There's 10nF MLCC immediately close to the bridge and another 100uF electrolytes further away. Trace width between gate and driver is approximately 60mm but nearly differential.
There is sufficient dead band of over 250ns and I am quite sure there is no overlap. Coss is rather small at 40pF and should play no major role in heating. Loss calculation by thermal techniques depict over 10W loss.
The issue here is Miller spike on the gates of the MOSFETs when the other MOSFET makes a transition. When the upper FET turns on, there is spike on the gate of the lower FET and vice versa. I have seen similar conditions earlier but the spikes in general are limited to less than a volt or two. But this time with this circuit the spikes are severe and measure over 5V. I understand that the probes must be exaggerating the spike but nevertheless it is very much present and 10W of loss confirms there's something wrong.
I have tried different values of gate resistor from 1 Ohm to 15 Ohm but it doesn't help. I have also used slow turn-on (15 ohm) and fast turn off (2 Ohm in series with diode) but again it doesn't help.
Any one with some sort of experience with this situation please share your views. Any help would be deeply appreciated.
I am posting images below:

(Lower MOSFET Vds-orange, Vgs-green)


(Upper MOSFET Vds-green, Vgs-orange)


(Vds rise and fall time)


(Vds negative transient during falling edge)


Thank you!

Starting with the last waveform, the "Vds negative transient" is physically implausible, it suggests that your probing method picks up large errors, probably common mode errors. Respectively it's questionable if the Vgs measurements are correct, particularly the oscillating part. Parasitic turn-on by Miller effect can surely happen, but it shouldn't with the reported low impedance gate drive, presuming a halfway regular layout.

No-load switching losses can be accurately determined by measuring bus current. Did you? According to a rough estimation, I would expect several W switching losses due to bridge hard switching at 100 kHz.

welcome to the real world of driving H bridges - what you have encountered is exactly normal - try putting a 1mH choke with a 2uF 630DC blocking cap across the H bridge - there will now be a small current in the fets when they turn off and no volts across the fet when they turn on - result = much less heating at no load - this is called ZVS switching ....!

- - - Updated - - -

just by way of example - 10W is 2.5W per fet = 0.5 C V^2 f, where f = 100kHz, V = 250V say, Ceff on each fet is therefore 800pF which sounds about right - every time a fet turns on it absorbs the energy in its Cout .... ( actually Ceff per fet = 400pF, you have two fets in a totem pole so 800pF charged to 250V for each fet turn on, discharging its own 400pF and charging the other one in the totem pole )

- - - Updated - - -

unless the Vds is zero (or very low) at turn on ...

The device datasheet gives a plot of Eoss vs Vds, it's about 1.6uJ at 250V. So with no load and 100kHz, you should see about 0.32W per FET of dissipation. Not enough to account for what you're seeing.

Cross conduction due to miller effect is plausible, since the Qgd of these FETs is greater than Qgs. In such a case, you must limit the dv/dt of the switching node. Ironically, one way to do this would be to add capacitance there, and your load inductance would aid in soft switching (on half of your edges, anyways). Another option is to use a bipolar gate drive.

What is the measured power observed from your PSU?

Hi,

Another option is to use a bipolar gate drive.

Click to expand...

I recommend this. Because adding capacitors or slowing down dV/dT will/may create additional loss, but in the (opposite) MOSFET.

IMHO: Eoss is the total energy stored in the gate capacitors. But I don´t think the whole energy is dissipated within the MOSFET. (Energy should never be dissipated by capacitors, anyway). The energy should be dissipated in the series gate resistance and in the gate_driver_resistance. so it will be divided in two parts.

But I agree, when calculating the worst case, one has to assume that all the energy is dissipated by the MOSFET.

****
I also think that the cause of the power dissipation is cross conduction.

--> Use a scope and measure the bus voltage. During cross conduction you will see a drop of V_bus.
Maybe one could use: Voltage_drop x ESR_Capacitor to estimate the current. (for short pulses)

Klaus

added:
Please show a photo of the circuit and/or schematic and PCB layout.

Thank you for the valuable replies.
I do not see any cross conduction, there is also no dip in the bus voltage which would insinuate cross-conduction. I have tested with dead-band as wide as 500ns but it doesn't help. If you refer to the 1st or second photo, you will notice that the Vds voltage transition only happens after about 200ns when the gate voltage has fallen down, this is because of the dead band.
To calculate power loss, I made external current flow through the diodes of the bridge using programmable power supply and noted the power absorption at which the bridge reached the same temperature at which it was running at no load. (105 degree C). The power loss is close to 10W. Today I also measured the DC bus current using Fluke-115 multimeter in DC current mode. It read 50mA almost independent of bus voltage (30V to 300V). I don't know how accurate this reading would be because the current pulses will be rather narrow and the multi-meter may show erroneous reading. Nevertheless at 250V, 50mA still corresponds to 12W which is close to that measured using temperature rise.
Today I replaced the MOSFETs with FCD380N60, which is a slightly slower MOSFET. The heating was lesser and the spike on the gate also was less. When I loaded one leg of the bridge with approx. 200mA current using resistive load, the heating reduced. At light load it heats up less than at no load.
Also, I understand that bipolar drive would be a great option. But is this a standard practice in the market? Up till now I did not need a bipolar driver. Perhaps the present gate driver is not as good?
Although it is rated 4A sink/source, I have seen many powerful gate drivers resulting in remarkably higher gate spike compared to weaker ones across different manufacturers.
ON semiconductor and IR drivers do a great job. TI is just about OK-ish in terms of spike absorption. This time I am using a Si-Labs driver.
Here is the schematic of the driver.

(Gate driver schematic)


Thank you

Hi,

If you refer to the 1st or second photo, you will notice that the Vds voltage transition only happens after about 200ns when the gate voltage has fallen down, this is because of the dead band.

Click to expand...

I don´t agree.
You can not see cross conduction nor can you see dead time in a scope picture with V_GS and V_DS.

You can see deadtime on a scope picture with both highside_V_GS and lowside_V_GS only.

It read 50mA almost independent of bus voltage (30V to 300V). I don't know how accurate this reading would be because the current pulses will be rather narrow and the multi-meter may show erroneous reading.

Click to expand...

You need a V_BUS_capacitor. If it´s a true DC-bus, then I recommend an electolytic bulk capacitor plus a fast ceramics capacitor very close at each highside_mosfet_drain.

The current measurement should be on the "supply side" of the bulk capacitor (not at the MOSFET side). Then the current is already low pass filtered and your current meter will show reliable average values.

Also, I understand that bipolar drive would be a great option.

Click to expand...

The SI8273 is a bipolar driver.

Klaus

added:
Please refer to datasheet Figure 3.1 regarding the power supply capacitors.
Also note that your R8 is not mentioned. I don´t think it causes the discussed problem, but it slows down charging of the bootstrap capacitors.
Did you strictly follow chapter 2.5 Layout Considerations?

KlausST said:

IMHO: Eoss is the total energy stored in the gate capacitors. But I don´t think the whole energy is dissipated within the MOSFET. (Energy should never be dissipated by capacitors, anyway). The energy should be dissipated in the series gate resistance and in the gate_driver_resistance. so it will be divided in two parts.

Click to expand...

Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.

- - - Updated - - -

mrinalmani said:

Today I also measured the DC bus current using Fluke-115 multimeter in DC current mode. It read 50mA almost independent of bus voltage (30V to 300V).

Click to expand...

Interesting. Note that in the datasheet, Eoss only changes from 1.1uJ to 1.6uJ as Vds increases from 30V to 250V, due to the severe nonlinearity of Coss. If your dissipation were entirely due to Eoss, then you might expect your power dissipation to rise by about 50% over that range. This would mean that your supply current would actually decrease as you increase Vds from 30V to 250V.

This is based on the assumption that, when each capacitor is charged, the FET that delivers that charge dissipates an amount of energy exactly equal to the capacitor's final energy (which is Eoss). When the capacitor is linear, this is always the case, regardless of the properties of the FET or how hard it is driven. However, if the capacitor is nonlinear, I don't think this applies. In particular, consider the process of charging a highly nonlinear Coss, like for your FET, from 0V to 250V. Nearly all of its charge is delivered by the time Vds reaches 30V. This means the high side FET delivering that charge did so while its Vds was over 200V, thus greatly increasing the energy it dissipates in the process. In this way, we can observe much higher power dissipation than predicted by the simple rule for linear capacitors.

This never occurred to me before, but I'm betting this is what's happening. A SPICE simulation would probably confirm this.

Great, now I have to redo all my spreadsheets....

Hi,

Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.

Click to expand...

You are correct. A little sketch helped me to see that the very most part of the energy is dissipated by the mosfet.

Klaus

When your fet turns on into a resistive load - the Vds falls and the Ids rises - there is a crossover conduction loss and the V & I cross over ( nothing to do with shoot thru ) this can be diminished by turning on faster.

There is also the Coss loss at turn on - from the data sheet ~ 2uJ at 280V, but there are two mosfets in the totem pole and the turning on mosfet also charges the other Coss in the process so each fet sees 4uJ x 100kHz = 0.4W x 4 = 1.6W + 8 watts from turning on the load.

We can make the turn on calc as follows, ave V = 250/2, Ave I = 1A / 2 = 0.5 amp say, turn on time = 30nS say, x 100kHz to get loss per fet.

TRY: putting 47k 2W across each fet ( 250VDC rail max ) this will halve the Vds at turn on ( 1/4 turn on losses) and see if the input power goes down at no load switching ( less resistor losses )

- - - Updated - - -

p.s. the ringing on your gate drive will contribute to power loss - better to sort that out ...

Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.

Click to expand...

Using Eoss for the loss estimation of transistors switching in bridge topology will seriously underestimate losses, due to the capacitance nonlinearity. A simulation with trustworthy nonlinear Coss model can show you why. While Vds is low and C(Vds) is low, most energy is dissipated by the opposite switch at Vbus-Vds.

FvM said:

Using Eoss for the loss estimation of transistors switching in bridge topology will seriously underestimate losses, due to the capacitance nonlinearity. A simulation with trustworthy nonlinear Coss model can show you why. While Vds is low and C(Vds) is low, most energy is dissipated by the opposite switch at Vbus-Vds.

Click to expand...

Yeah, I just realized this, see above. Also confirmed it with a simple SPICE simulation.

mtwieg said:

The device datasheet gives a plot of Eoss vs Vds, it's about 1.6uJ at 250V. So with no load and 100kHz, you should see about 0.32W per FET of dissipation. Not enough to account for what you're seeing.

Cross conduction due to miller effect is plausible, since the Qgd of these FETs is greater than Qgs. In such a case, you must limit the dv/dt of the switching node. Ironically, one way to do this would be to add capacitance there, and your load inductance would aid in soft switching (on half of your edges, anyways). Another option is to use a bipolar gate drive.

What is the measured power observed from your PSU?

Click to expand...

I'd be careful, energy stored by one mosfet isn't the same as energy dissipated by the complimentary mosfet when the C is non-linear..and mosfet C is very non-linear.


I also suspect that there may be 'nothing wrong'. This may be a case of hard switched losses coming in higher than expected...it's happened to me. 250V is a lot different than a 5V buck converter and devices designed for high voltage have additional parasitics (like reverse recovery)
https://www.edaboard.com/showthread.php?370433-Zero-Load-Switching-Losses

You can 'see' shoot through by looking for droop spikes on the bridge input voltage or see it easily with a good current probe.

Hi everyone, thanks for the replies
There is no shoot through for sure, I increased the dead-band to 400ns to make sure about this.
As just pointed out by @mtwieg and then again by @FvM, the charge delivered to Coss of a MOSFET happens through a much higher voltage across the complementary pair and therefore greater loss is expected. Now this never came to my mind, but surely seems like a very valid reason. I haven't also come across any literature earlier that discusses this point. I am very interested to explore the possibilities for this type of switching behavior. But before jumping in directly I just wanted to make sure that there's absolutely 0% chance of shoot-through or Miller turn ON.
Now shoot-through is not present for sure and there was a doubt about Miller turn-ON since the probe picked up spikes on the gate. This may have been a common mode spike or real but exaggerated spike, I am not sure. So I decided to drive the gate to negative voltage. I added two small isolated power modules on top of the PCB and made some modifications and managed to get +12V and -14V at both the gates of one leg of the bridge. I completely removed the other leg for easier analysis.
Here are the results:
VGS is orange and swings around -12V. VDS is green and 100V/div

(Low side FET VGS, VDS)


(Low side FET VGS, VDS)


(Low side FET VGS, VDS)


(High side FET VGS, VDS)


(High side FET VGS, VDS)


(High side FET VGS, VDS)


By looking at the figures it is clear that the Miller spike does not cross threshold of the MOSFETs. But interestingly this does no good to the heating problem. Heating is still present and very much the same!
Today I tested FCD380N60 MOSFETs at 300V, 100KHz, 2Ohm gate resistor and power loss was 2.9W per switch, total 5.8W. Again confirmed by temperature rise method and this by direct thermocouple probing at MOSFETs. (Last time it was by IR thermometer)

put a 1mH choke in series with a 2uF cap ( suitably rated ) across the H bridge and see if the no load losses come down ...

I think you've eliminated shoot-through as a possible cause. That really leaves the Eoss losses. This is why soft switching is important at high voltages. Depending on what your load is, getting ZVS on all edges may be feasible.

This is one of the reasons I make spreadsheets when choosing components and operating frequency. It may turn out that using a FET with lower Eoss and higher Ron gives lower losses overall.