Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

MOS switches in FeedForward Equalizer (FFE) for SERDES for 112GBPS

Status
Not open for further replies.
P

pankajpc

Junior Member level 1
Joined
Aug 22, 2014
Messages
19
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,283
Activity points
1,436
Hi All,

I was wondering as to how to design CMOS switches for FFE for SERDES in 112GBPS. It is a quarter rate architecture. I am using PRBS data pattern but the switch is showing more output at sampling node (Node after sampling switch. where the sampling capacitor is put) then at the output of Source follower resistor (75 ohm) / CTLE/VGA which is after the PRBS input.

Is it possible that it may not be possible to do the same as we may have reached a fundamental physics limit.

Can you please share your opinion.

regards
-pankaj
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top