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  1. #1
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    Critical path while using xilinx ise

    Dear all,
    When i tried to synthesize my verilog code in ISE, my timing report said,

    Minimum period: 4.490ns (Maximum Frequency: 222.712MHz)
    Minimum input arrival time before clock: 4.358ns
    Maximum output required time after clock: 0.728ns
    Maximum combinational path delay: No path found

    From what i understand, Maximum frequency is determined by the path that takes a longer time to execute. How do i trace that path?

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  2. #2
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    barry's Avatar
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    Re: Critical path while using xilinx ise

    Your timing report should identify your slowest path.



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  3. #3
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    Re: Critical path while using xilinx ise

    Where do i check that? In the synthesis report right?



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