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  1. #1
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    vivado post route simulation problem

    Hello,
    I am trying to perform post implementation timing simulation of attached circuit in vivado 2016.2(). I am able to do behavioral simulation with all the objects visible (pls refer attached eda_bs). But when i start post implementation timing simulation, i am unable to see d[0:7] listed in objects tab(pls refer attached eda_pits).

    Anyone can guess the reason?

    code:

    Code VHDL - [expand]
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    entity TV is
        Port ( clk : in  STD_LOGIC;
               en : in  STD_LOGIC;
               rst : in  STD_LOGIC;
               q : out  STD_LOGIC_VECTOR (0 to 7));
    end TV;
     
    architecture Behavioral of TV is
    component dff is
        Port ( d : in  STD_LOGIC;
               clk : in  STD_LOGIC;
               rst : in  STD_LOGIC;
               q : out  STD_LOGIC);
    end component;
     
     
    attribute keep : string;  
    signal d:std_logic_vector(0 to 7);
    attribute keep of d : signal is "true";  
      
     
     
    begin
     
    l1: dff port map (d(0),clk,rst,q(0));
    d(0)<= clk and en;
     
    l2:dff port map (d(1),clk,rst,q(1));
    d(1)<= d(0) and en;
     
    l3:dff port map (d(2),clk,rst,q(2));
    d(2)<= d(1) and en;
     
    l4:dff port map (d(3),clk,rst,q(3));
    d(3)<= d(2) and en;
     
    l5:dff port map (d(4),clk,rst,q(4));
    d(4)<= d(3) and en;
     
    l6:dff port map (d(5),clk,rst,q(5));
    d(5)<= d(4) and en;
     
    l7:dff port map (d(6),clk,rst,q(6));
    d(6)<= d(5) and en;
     
    l8:dff port map (d(7),clk,rst,q(7));
    d(7)<= d(6) and en;
     
     
    end Behavioral;




    Testbench


    Code VHDL - [expand]
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    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --USE ieee.numeric_std.ALL;
     
    ENTITY tb IS
    END tb;
     
    ARCHITECTURE behavior OF tb IS 
     
        -- Component Declaration for the Unit Under Test (UUT)
     
        COMPONENT TV
        PORT(
             clk : IN  std_logic;
             en : IN  std_logic;
             rst : IN  std_logic;
             q : OUT  std_logic_vector(0 to 7)
            );
        END COMPONENT;
        
     
       --Inputs
       signal clk : std_logic := '0';
       signal en : std_logic := '0';
       signal rst : std_logic := '1';
     
        --Outputs
       signal q : std_logic_vector(0 to 7);
     
       -- Clock period definitions
       constant clk_period : time := 10 ns;
     
    BEGIN
     
        -- Instantiate the Unit Under Test (UUT)
       uut: TV PORT MAP (
              clk => clk,
              en => en,
              rst => rst,
              q => q
            );
     
       -- Clock process definitions
       clk_process :process
       begin
            clk <= '0';
            wait for clk_period/2;
            clk <= '1';
            wait for clk_period/2;
       end process;
     
     
       -- Stimulus process
       stim_proc: process
       begin        
          -- hold reset state for 100 ns.
          wait for 100 ns;  
    rst<='0';
    en<='1';
     
          wait for clk_period*10;
     
          -- insert stimulus here 
     
          wait;
       end process;
     
    END;
    Last edited by ads-ee; 8th July 2019 at 20:00. Reason: added code tags

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  2. #2
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    Re: vivado post route simulation problem

    The signals are getting optimized away. You need to use some attributes (look it up) like KEEP in order to preserve those signals. But unless you have a really good reason to do that, you may degrade performance.


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  3. #3
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    Re: vivado post route simulation problem

    I think i have already used KEEP in the code(please refer the code above). If that is not how it is done, please tell the correct way if possible....technology schematic looks ok(with above code) too....The same design i have tried to simulate using ISE 14.5. It shows all the objects.
    It need to see the same on vivado 2016.2.



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    Re: vivado post route simulation problem

    A synthesis log is always generated by Vivado. Have you checked that thoroughly? That's a fiest check.
    Can you see the signal d[0:7] there?
    FPGA enthusiast!



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  5. #5
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    Re: vivado post route simulation problem

    I’m not going to unzip your file, but where is your component “diff”? Is it properly included in your project?



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  6. #6
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    Re: vivado post route simulation problem

    hello dpaul,
    this is what i got from the log.

    Code:
    Start Writing Synthesis Report
    ---------------------------------------------------------------------------------
    
    Report BlackBoxes: 
    +-+--------------+----------+
    | |BlackBox name |Instances |
    +-+--------------+----------+
    +-+--------------+----------+
    
    Report Cell Usage: 
    +------+-----+------+
    |      |Cell |Count |
    +------+-----+------+
    |1     |BUFG |     1|
    |2     |LUT2 |     8|
    |3     |FDRE |     8|
    |4     |IBUF |     3|
    |5     |OBUF |     8|
    +------+-----+------+
    
    Report Instance Areas: 
    +------+---------+-------+------+
    |      |Instance |Module |Cells |
    +------+---------+-------+------+
    |1     |top      |       |    28|
    |2     |  l1     |dff    |     1|
    |3     |  l2     |dff_0  |     1|
    |4     |  l3     |dff_1  |     1|
    |5     |  l4     |dff_2  |     1|
    |6     |  l5     |dff_3  |     1|
    |7     |  l6     |dff_4  |     1|
    |8     |  l7     |dff_5  |     1|
    |9     |  l8     |dff_6  |     1|
    +------+---------+-------+------+
    ---------------------------------------------------------------------------------
    Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 466.059 ; gain = 259.000
    ---------------------------------------------------------------------------------
    Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
    Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 466.059 ; gain = 239.672
    Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 466.059 ; gain = 259.000
    INFO: [Project 1-571] Translating synthesized netlist
    INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
    INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
    INFO: [Project 1-570] Preparing netlist for logic optimization
    INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    INFO: [Project 1-111] Unisim Transformation Summary:
    No Unisim elements were transformed.
    
    INFO: [Common 17-83] Releasing license: Synthesis
    22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
    synth_design completed successfully
    synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 564.609 ; gain = 340.313
    report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 564.609 ; gain = 0.000
    INFO: [Common 17-206] Exiting Vivado at Wed Jul 03 00:12:58 2019...

    any help?

    - - - Updated - - -

    Quote Originally Posted by barry View Post
    I’m not going to unzip your file, but where is your component “diff”? Is it properly included in your project?
    Hello barry,
    Thanks for your time. I think yes. It is properly included.
    Last edited by ads-ee; 8th July 2019 at 20:00. Reason: added tags



  7. #7
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    Re: vivado post route simulation problem

    That's doesn't look like the complete synth log file.
    Look into project_name.runs/synth_1/runme.log
    FPGA enthusiast!



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    Re: vivado post route simulation problem

    Quote Originally Posted by dpaul View Post
    That's doesn't look like the complete synth log file.
    Look into project_name.runs/synth_1/runme.log
    Hello dpaul,
    following is the file. Also attaching post implementation simulation snap-shot for reference.



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    Re: vivado post route simulation problem

    Your synth log says there are no timing constraints for your design.
    What are you trying to do?
    FPGA enthusiast!



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    Re: vivado post route simulation problem

    Quote Originally Posted by dpaul View Post
    Your synth log says there are no timing constraints for your design.
    What are you trying to do?
    Hello dpaul,
    You mean i won't see the objects (d[0:7]) till i give constraints to the design? Actually, i am unable to see d[0:7] in objects tab (Mentioned in the code above)



  11. #11
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    Re: vivado post route simulation problem

    Quote Originally Posted by dpaul View Post
    Your synth log says there are no timing constraints for your design.
    What are you trying to do?
    Timing constraints have nothing to do with the visibility of signals in simulation.



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    Re: vivado post route simulation problem

    Timing constraints have nothing to do with the visibility of signals in simulation.
    The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design constraints?
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  13. #13
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    Re: vivado post route simulation problem

    Quote Originally Posted by dpaul View Post
    The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design constraints?
    There's nothing intrinsically wrong with doing this. It's not necessarily a good idea if you actually HAVE some constraints, i.e., minimum frequency, but it has nothing to do with signal visibility. I'm guessing there's some optimization going on that's removing his signals.



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  14. #14
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    Re: vivado post route simulation problem

    Use the attribute dont_touch on the module instead of keep. Synthesis will adhere to the keep attribute but the implementation tools will ignore it. The attribute dont_touch won't allow a signal to be optimized at all.

    I just noticed that the code:

    Code VHDL - [expand]
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    d(0)<= clk and en;
    d(1)<= d(0) and en;
    d(2)<= d(1) and en;
    d(3)<= d(2) and en;
    d(4)<= d(3) and en;
    d(5)<= d(4) and en;
    d(6)<= d(5) and en;
    d(7)<= d(6) and en;

    ends up as:
    Code VHDL - [expand]
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    d(0) <= clk and en;
    --            d(0)
    d(1) <= (clk and en) and en;
    --            d(1)
    d(2) <= (clk and en and en) and en;
    --...
    so the end result is all of the d(#) are just clk and en with an extra LUT delay between each d.

    Not sure what the point of this code is, but relying on LUT delays as some sort of delay line detection method is a sure way to end up with a design that sometimes works and sometimes doesn't depending on the placement of logic after implementation.


    1 members found this post helpful.

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