sandeep_sggs
Full Member level 2
Hello,
I am trying to perform post implementation timing simulation of attached circuit in vivado 2016.2(). I am able to do behavioral simulation with all the objects visible (pls refer attached eda_bs). But when i start post implementation timing simulation, i am unable to see d[0:7] listed in objects tab(pls refer attached eda_pits).
Anyone can guess the reason?
code:
Testbench
I am trying to perform post implementation timing simulation of attached circuit in vivado 2016.2(). I am able to do behavioral simulation with all the objects visible (pls refer attached eda_bs). But when i start post implementation timing simulation, i am unable to see d[0:7] listed in objects tab(pls refer attached eda_pits).
Anyone can guess the reason?
code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 entity TV is Port ( clk : in STD_LOGIC; en : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC_VECTOR (0 to 7)); end TV; architecture Behavioral of TV is component dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end component; attribute keep : string; signal d:std_logic_vector(0 to 7); attribute keep of d : signal is "true"; begin l1: dff port map (d(0),clk,rst,q(0)); d(0)<= clk and en; l2:dff port map (d(1),clk,rst,q(1)); d(1)<= d(0) and en; l3:dff port map (d(2),clk,rst,q(2)); d(2)<= d(1) and en; l4:dff port map (d(3),clk,rst,q(3)); d(3)<= d(2) and en; l5:dff port map (d(4),clk,rst,q(4)); d(4)<= d(3) and en; l6:dff port map (d(5),clk,rst,q(5)); d(5)<= d(4) and en; l7:dff port map (d(6),clk,rst,q(6)); d(6)<= d(5) and en; l8:dff port map (d(7),clk,rst,q(7)); d(7)<= d(6) and en; end Behavioral;
Testbench
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT TV PORT( clk : IN std_logic; en : IN std_logic; rst : IN std_logic; q : OUT std_logic_vector(0 to 7) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal en : std_logic := '0'; signal rst : std_logic := '1'; --Outputs signal q : std_logic_vector(0 to 7); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: TV PORT MAP ( clk => clk, en => en, rst => rst, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; rst<='0'; en<='1'; wait for clk_period*10; -- insert stimulus here wait; end process; END;
Attachments
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