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  1. #1
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    Totem pole pfc challenges

    I've done a few boost PFC front ends, but am now looking at maybe giving the totem pole PFC a try. A brief literature search shows that it has many caveats, most of which derive from the fact that the AC line alternates between clamping to each side of the DC output bus at zero crossings.
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    It occurred to me that one way to get around this issue would be to replace the two low frequency FETs/diodes (Q3/Q4) with high frequency GaN/SiC FETs. Then split the main boost inductor between each line, treating both sides the same. You would be able to freely choose the common mode voltage of the DC bus relative to earth, or at the very least remove the large jumps that normally happen at every zero crossing.

    The downside would be that those two extra high frequency FETs now have similar switching losses as the original two, so you would see a those switching losses approximately double. On the other hand, you could interleave the PWM phase of each leg, thus allowing for a smaller overall boost choke, and possible a smaller EMI filter.

    Surely this isn't a new idea, but I don't know if it has a name (active bridge PFC?), and I can't find any literature on it.

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    Re: Totem pole pfc challenges

    I'm not sure from where you come and where you want to go to.

    The shown topology, despite of some asymmetry by apparently using different switch types, is basically a four-quadrant boost converter, often named active front end. It can source and sink active or reactive power, operate as PFC rectifier as well as grid tied inverter supplying power to the net.

    The more simple two quadrant PFC can be build with two active switches and two diodes, loosing the feature of sinking reactive power or even to recuperate.

    I understand that your initial circuit uses slow switches for Q3 and Q4 and can work well an asymmetrical boost inductor with EMI issues. A symmetrically operated bridge would use an unipolar modulation scheme and has better control near the zero crossings. As mentioned, it probably takes advantage from splitting the boost inductor, looking like 2/3 of a three phase active front end.

    Active H bridges are frequently used for single phase grid tied inverters. There has been the famous "Little Box Challenge" three years ago, presenting many circuits of this kind.


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    Re: Totem pole pfc challenges

    Right, I didn't really state the fundamental problems. Lets use Vout_dm and Vout_cm to refer to the differential and common mode components of Vout, respectively. Cy is the capacitor connecting Vout to PE.

    With a standard PFC, Vout_cm looks like the classic half-wave rectified sine wave with amplitude of Vac. With the totem pole PFC, Vout_cm is a square wave with amplitude equal to Vout_dm. My main issue with this is earth leakage currents produced. If Vac=240V, f=60Hz, and Cy=1nF, then the standard and totem pole PFCs create 65uA and 240uA of leakage current, respectively (measured as per IEC 601-1), and that alone exceeds the limits imposed by some standards. The low frequency of this leakage current means it can't be dealt with by reasonable common mode filters, and decreasing that Y cap is not always an option.

    My idea is to PWM both sides of the mains at high frequency so that Vout_cm can be controlled somewhat arbitrarily (the low frequency component of Vout_cm, anyways). I suppose another way of looking at it is shifting the low frequency content of Vout_cm into a much higher frequency band, thus allowing a reasonable CM filter to attenuate it. Of course this might present an issue for conducted EMC compliance. But as-is, it seems like the totem pole pfc isn't suited to applications where low leakage is required (medical).



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    Re: Totem pole pfc challenges

    Are you sure you want to use Y capacitors at all? How about a double screened transformer without any Y capacitors? There will be still a certain screen-to-screen capacitance, but hopefully below 100 pF.



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    Re: Totem pole pfc challenges

    Quote Originally Posted by FvM View Post
    Are you sure you want to use Y capacitors at all? How about a double screened transformer without any Y capacitors? There will be still a certain screen-to-screen capacitance, but hopefully below 100 pF.
    That was my initial plan. I wound transformers of my own with single and double screens added, and dropped those into a PSFB dev kit. It only seemed to lower emissions by about 6dB (in the frequency range of highest emissions, anyways), so not as effective as I had hoped. It's possible that much of the remaining conducted EMI is coming from other components in the dev kit though (it uses gate drive transformers, and a small flyback for aux power).



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    Re: Totem pole pfc challenges

    Here are a bunch of comments.

    The totem pole PFC can be seen as an inverter or full bridge class-D run backwards. Lots of references for these applications are applicable.

    Note that the total leakage charge isn't vastly different. You have to charge the common mode C (Ccm) to Vout_dm (your term, I'll call it Vpfc) instead of Vac rectified. Separately the current will come in large pulses at the zero crossing for the totem pole. Is one, the other or both your main concern?

    In terms of control I see three major options.
    1) The 'standard' asymetric totem pole pfc control scheme
    2) Two high frequency half-bridges but only use one at a time: each 'draws' a half wave while the other shorts its low-side fet.
    3) What I think you're proposing: Run both half bridges all the time in a class-D style complimentary fashion which has zero common mode component

    Pros/Cons for above
    1) Cheaper fets and you don't need filtering on the LF leg. 1X switching loss. Big slug of CM current
    2) Needs filtering on both legs. Should have similar common current profile to standard boost PFC. 1X switching loss
    3) No common mode component but 2X switching loss. 2X switching voltage is presented to filter. But two half-bridges can be interleaved.

    All of these are common for different applications but I haven't seen 2 or 3 referenced for PFC designs. Have you considered buying any totem pole demo boards. Transphorm, Gan Systems, Ti etc make them.
    https://www.digikey.com/products/en?...TP2500P100-KIT

    Other ideas I've toyed around with:
    -The LF leg can be soft switched to reduce the CM current slug
    -The LF leg could be eliminated entirely: AC couple instead


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    Re: Totem pole pfc challenges

    Quote Originally Posted by asdf44 View Post
    Here are a bunch of comments.

    The totem pole PFC can be seen as an inverter or full bridge class-D run backwards. Lots of references for these applications are applicable.

    Note that the total leakage charge isn't vastly different. You have to charge the common mode C (Ccm) to Vout_dm (your term, I'll call it Vpfc) instead of Vac rectified. Separately the current will come in large pulses at the zero crossing for the totem pole. Is one, the other or both your main concern?
    Yes, the peak to peak Vout_cm is not very different between the two circuits. But leakage is measured in RMS, and as you mentioned, the leakage current from the totem pole comes in sharp pulses. This gives a measured leakage current about 4x higher.
    In terms of control I see three major options.
    1) The 'standard' asymetric totem pole pfc control scheme
    2) Two high frequency half-bridges but only use one at a time: each 'draws' a half wave while the other shorts its low-side fet.
    3) What I think you're proposing: Run both half bridges all the time in a class-D style complimentary fashion which has zero common mode component

    Pros/Cons for above
    1) Cheaper fets and you don't need filtering on the LF leg. 1X switching loss. Big slug of CM current
    2) Needs filtering on both legs. Should have similar common current profile to standard boost PFC. 1X switching loss
    3) No common mode component but 2X switching loss. 2X switching voltage is presented to filter. But two half-bridges can be interleaved.
    #2 is an interesting suggestion. In my simulation so far, I've seen that whenever I put some filter inductance on both legs, it leads to much larger common mode EMI. I suppose that's to be expected, because that inductor allows Vout_cm to swing freely against PE at high frequencies.

    Another simple option occurs to me:
    4) Replace the two slow FETs in the totem pole with an active full bridge of slow FETs. What you end up with is basically a traditional boost PFC, with a synchronous rectifier boost. Two more slow FETs in the conduction path than the totem pole, but without the larger leakage.

    All of these are common for different applications but I haven't seen 2 or 3 referenced for PFC designs. Have you considered buying any totem pole demo boards. Transphorm, Gan Systems, Ti etc make them.

    https://www.digikey.com/products/en?...TP2500P100-KIT
    A colleague of mine is tinkering with one of these, I think. As Easy_peasy has mentioned previously, these dev kits totally gloss over EMI and leakage.
    Other ideas I've toyed around with:
    -The LF leg can be soft switched to reduce the CM current slug
    Yes, I thought that maybe adding a large capacitance to the slow FETs (like >1uF) might help. Haven't tried simulating it.
    -The LF leg could be eliminated entirely: AC couple instead
    You mean with a transformer or blocking capacitor? That would be bigger than the rest of the supply itself.



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  8. #8
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    Re: Totem pole pfc challenges

    Quote Originally Posted by mtwieg View Post
    #2 is an interesting suggestion. In my simulation so far, I've seen that whenever I put some filter inductance on both legs, it leads to much larger common mode EMI. I suppose that's to be expected, because that inductor allows Vout_cm to swing freely against PE at high frequencies.
    My mind spun through this thought as well. The second inductor 'undefines' your pfc_gnd compared to the 'standard' implementation where the LF bridge is always tying it to one AC line. On the other hand that's exactly what a CM choke does...

    Note that if you consider this an inverter or class-D run backwards you can see that you could add output (input in this case) filter caps on the AC line to your ground. Take your control outside the caps and they'll be hidden from the outside world.

    Quote Originally Posted by mtwieg View Post
    Another simple option occurs to me:
    4) Replace the two slow FETs in the totem pole with an active full bridge of slow FETs. What you end up with is basically a traditional boost PFC, with a synchronous rectifier boost. Two more slow FETs in the conduction path than the totem pole, but without the larger leakage.
    Right so just a synchronous boost with a synchronous rectifier. I don't recall seeing this, all the GaN/SiC people trumpet the 'standard' totem pole, so I wonder if its worth it but it should work fine.

    A colleague of mine is tinkering with one of these, I think. As Easy_peasy has mentioned previously, these dev kits totally gloss over EMI and leakage.
    You might want to see for yourself. The Transphorm one is almost dominated by its input filtering.

    Yes, I thought that maybe adding a large capacitance to the slow FETs (like >1uF) might help. Haven't tried simulating it.
    You mean with a transformer or blocking capacitor? That would be bigger than the rest of the supply itself.
    These are probably more bad ideas but I simulated both quickly and saw some stuff that worked. To AC couple the LF leg I split the bulk PFC capacitance in the middle and returned to that (yep this would be costly in real life..)

    On the other hand a simple implementation with diodes replacing the LF fets and largish caps across them to soft switch the LF node seems somewhat appealing. It avoids figuring out the right dead time. At light loads it may act AC coupled - never reaching a rail and turning on the diodes, but not a big deal.



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    Re: Totem pole pfc challenges

    Still thinking about this?

    I'm curious what your thoughts are.



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