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  1. #1
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    How to read a single 64bit value in 2 clock cycles in verilog

    I want to read a 64bit input in 2 clock cycles. i.e. 32bit in 1 clock cycle and the remaining 32bits in 2nd clock cycle. the 32bit is divided into 8bit which serve as input for 4x1 Mux. So 32bit is being read using Mux. But how to read a whole value in 2 clock cycles can someone guide me with it please.

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  2. #2
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    Re: How to read a single 64bit value in 2 clock cycles in verilog

    what?

    Cycle one: read 32 bits
    Cycle two: read the other 32 bits
    Done.

    What's your real question? Do you have any particular hardware in mind, or are you just reading random bits out of the air?

    If you've got 64 bits sitting on a port, where's your problem in reading the lower 32 bits and then the upper 32?



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  3. #3
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    Re: How to read a single 64bit value in 2 clock cycles in verilog

    I would expect two 32 bit registers sampling the input data. Further data processing can be delayed according to your needs which are not very clear yet.



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