Keypad saved number display shift left in Verilog

cmyang · Jun 28, 2019

I'm designing a number exchange module, and so far I've been able to make it display on Seven Segment Display (S-S-D), like if I press 0 it shows 0... etc. I'm using 2 sets of 4-bits S-S-D (Common Anode).

Now I want to do like:

default states :

Code:

0000_0000

Now if I press 1 :

Code:

0000_0001

If I press 2 :

Code:

0000_0012

etc.
Whichever key I press, the display will not erase the already displaying number, it will shift it to the left...

And when all 8 S-S-D is full of displaying numbers like:

Code:

486C_8763

, at this moment, when I press a key enter a number,
like 1 it should be like :

Code:

 86C8_7631

; it should keep shifting to the left.

Here's my attempted code, and only been able to display it on S-S-D, and display all S-S-D

Code:

 0000_0000

... still not able to do what's been describe above...

Code Verilog - [expand]
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module keydata (clk,scano,keyin,keyout,SegOut);
input clk;
reg dclk;
 
output reg [3:0]keyout=4'b1110;
input [3:0]keyin;
output reg [7:0]SegOut;
output reg [7:0]scano;
integer z1=0,zz=0;
 
reg [7:0]bcdz;
reg [2:0]scan;
reg [25:0]clkin=0;
reg clkindown;
reg state;
reg [7:0]bcdz_t;
 
always@(posedge clk)
begin
    clkin<=clkin+1;
    clkindown<=clkin[22];
end
always@(posedge clkindown)
begin
    scan<=scan+1;
end
 
always@(posedge clk)
begin
 
//---------------------
if(z1==50000)
    begin
    z1<=0;
    keyout<={keyout[2:0],keyout[3]};//1110->1101->1011->0111->1110(loop)
    end
else
    z1<=z1+1;
//---------------------
    
    
//---------------------
if(zz==10000)
    begin
    zz<=0;
    dclk<=~dclk;
    end
else
    zz<=zz+1;
//--------------------- 
end
 
always@(posedge clkindown)
    begin
        case(scan)
                0: scano<=8'b1111_1110;
                1: scano<=8'b1111_1101;
                2: scano<=8'b1111_1011;
                3: scano<=8'b1111_0111;
                4: scano<=8'b1110_1111;
                5: scano<=8'b1101_1111;
                6: scano<=8'b1011_1111;
                7: scano<=8'b0111_1111;
            default: scano<=8'hFF;
        endcase
    end
 
always@(posedge dclk) 
begin
 
 
    if (keyout==4'b1110)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b1100;//C
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b1101; //D
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b1110; //E
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b1111;//F
            end
        end
        
    else if (keyout==4'b1101)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b1000; //8
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b1001; //9
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b1010; //A
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b1011; //B
            end
        end
        
    else if (keyout==4'b1011)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b0100; //4
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b0101; //5
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b0110; //6
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b0111; //7
            end
        end
        
    else if (keyout==4'b0111)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b0000; //0
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b0001; //1
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b0010; //2
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b0011; //3
            end
        end
    end
 
always@(bcdz or state)
begin
    case(bcdz)
            0   :   case(state)
                            0   :begin SegOut <=   8'hC0;   state <= 1; end
                            1   :        SegOut <=   8'hC0;
                    endcase
            1   :   case(state)
                            0   :begin SegOut <=   8'hF9;   state <= 1; end
                            1   :        SegOut <=   8'hF9;
                    endcase
            2   :   case(state)
                            0   :begin SegOut <=   8'hA4;   state <= 1; end
                            1   :        SegOut <=   8'hA4;
                    endcase
            3   :   case(state)
                            0   :begin SegOut <=   8'hB0;   state <= 1; end
                            1   :      SegOut <=   8'hB0;
                    endcase
            4   :   case(state)
                            0   :begin SegOut <=   8'h99;   state <= 1; end
                            1:           SegOut <=   8'h99;
                    endcase
            5   :   case(state)
                            0   :begin SegOut <=   8'h92;   state <= 1; end
                            1:           SegOut <=   8'h92;
                    endcase
            6   :   case(state)
                            0   :begin SegOut <=   8'h82;   state <= 1; end
                            1:      SegOut <=   8'h82;
                    endcase
            7   :   case(state)
                            0   :begin SegOut <=   8'hF8;   state <= 1; end
                            1:          SegOut <=   8'hF8;
                    endcase
            8   :   case(state)
                            0   :begin SegOut <=   8'h80;   state <= 1; end
                            1:           SegOut <=   8'h80;
                    endcase
            9   :   case(state)
                            0   :begin SegOut <=   8'h98;   state <= 1; end
                            1:           SegOut <=   8'h98;
                    endcase
            10 :    case(state)
                            0   :begin SegOut <=   8'h88;   state <= 1; end
                            1:           SegOut <=   8'h88;
                    endcase
            11  :   case(state)
                            0   :begin SegOut <=   8'h83;   state <= 1; end
                            1:           SegOut <=   8'h83;
                    endcase
            12  :   case(state)
                            0   :begin SegOut <=   8'hC6;   state <= 1; end
                            1:           SegOut <=   8'hC6;
                    endcase
            13  :   case(state)
                            0   :begin SegOut <=   8'hA1;   state <= 1; end
                            1:           SegOut <=   8'hA1;
                    endcase
            14  :   case(state)
                            0   :begin SegOut <=   8'h86;   state <= 1; end
                            1:          SegOut <=   8'h86;
                    endcase
            15 :    case(state)
                            0   :begin SegOut <=   8'h8E;   state <= 1; end
                            1:          SegOut <=   8'h8E;
                    endcase
            default :   SegOut <= 8'hFF;
    endcase
end
 
endmodule

KlausST · Jun 28, 2019

Hi,

please understand that it takes a lot of time to understand your undocumented code.

Maybe you should give some more information /documentation to your code.

Klaus

ads-ee · Jun 28, 2019

Your main issues is you don't seem to have any code to store each digit as they are input and perform the bcd-to-7seg conversion on each of those digits. That storage of the input digits is the shift register you require to make the display scroll. The scan should be indexing through those stored digits to display them on the appropriate 7seg display.

It's obvious that you don't know what your circuit is supposed to look like and instead just started writing Verilog code. As you are describing hardware you need to have a good idea what you are trying to build before writing any code.

You need to rethink what state is supposed to do as of right now it does nothing since the assignment for SegOut is the same regardless of the state value. You should also rethink using 3 clock domains for a design that should only have 1. Use the input clock and an enable to update registers slower than the input clock rate. Also document your code with comments if you expect anyone to help, besides that it will help you when you have to look at your own code after a few months or years later.

cmyang · Jun 28, 2019

KlausST said:
Hi,

please understand that it takes a lot of time to understand your undocumented code.

Maybe you should give some more information /documentation to your code.

Klaus

My apologies,I posted in a hurry,forgot to add the annotation,Here I've added some annotates to each part of codes.
I hope these annotates helps you to analyzing to assist me,thanks...

ads-ee said:
Your main issues is you don't seem to have any code to store each digit as they are input and perform the bcd-to-7seg conversion on each of those digits. That storage of the input digits is the shift register you require to make the display scroll. The scan should be indexing through those stored digits to display them on the appropriate 7seg display.

It's obvious that you don't know what your circuit is supposed to look like and instead just started writing Verilog code. As you are describing hardware you need to have a good idea what you are trying to build before writing any code.

You need to rethink what state is supposed to do as of right now it does nothing since the assignment for SegOut is the same regardless of the state value. You should also rethink using 3 clock domains for a design that should only have 1. Use the input clock and an enable to update registers slower than the input clock rate. Also document your code with comments if you expect anyone to help, besides that it will help you when you have to look at your own code after a few months or years later.

First.My apologies,I posted in a hurry,forgot to add the annotation,Here I've added some annotates to each part of codes.
And yes,at this part of circuit design,I'm still quite fuzzy about it,completely lost and have no idea how to continuing,
I can't see the whole big picture,So that's why I'm here to ask a different opinion or approach.

Though,I know I need a state machine to do something about the stored key value,and use state machine to output them on the 7seg,when pressed and scroll it when press next key...
I understand part of the ideas,but just have no idea how to write it/implement it.

Code Verilog - [expand]
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module keydata 
(
  input clk, //input clk 50MHz
  output reg [3:0]keyout=4'b1110, //Default scan value 4bits 
  input [3:0]keyin, //Keypad receive value
  output reg [7:0]SegOut, //Seven Segment Display output
  output reg [15:0]scano //Seven Segment Display Scans
);
 
integer z1=0,zz=0; //Registers for frequency dividing
reg dclk; //Divided frequency clock
reg [7:0]bcdz; //register for saving keypad's number value
reg [3:0]scan; //scan states
 
 
always@(posedge clk)
begin
 
//---------------------
if(z1==50000)   //frequency divider 
    begin
    z1<=0;
    scan<={scan[2:0],scan[3]}; //scanning pattern shifting resgister
    keyout<={keyout[2:0],keyout[3]};  //keypad column scanning 1110->1101->1011->0111->1110(loop)
    end
else
    z1<=z1+1;
//---------------------
    
    
//---------------------
if(zz==10000) //frequency divider for scanning
    begin
    zz<=0;
    dclk<=~dclk;
    end
else
    zz<=zz+1;
//--------------------- 
end
 
always@(posedge dclk)  //Seven Segment Scanning
    begin
        case(scan)
                0: scano<=scano[3:0];
                1: scano<=scano[7:4];
                2: scano<=scano[11:8];
                3: scano<=scano[15:12];
        endcase
    end
 
always@(posedge dclk) //4x4 Keypad detecting 
begin
 
 
    if (keyout==4'b1110) //Detecting which keyout is currently at scanning
        begin
        if(keyin==4'b0111) //Tell which key it is
            begin
            bcdz<=4'b1100;//C //the key's value,save by a register
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b1101; //D
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b1110; //E
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b1111;//F
            end
        end
        
    else if (keyout==4'b1101) //Using [B]else if[/B] to differentiate priorities.
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b1000; //8
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b1001; //9
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b1010; //A
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b1011; //B
            end
        end
        
    else if (keyout==4'b1011)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b0100; //4
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b0101; //5
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b0110; //6
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b0111; //7
            end
        end
        
    else if (keyout==4'b0111)
        begin
        if(keyin==4'b0111)
            begin
            bcdz<=4'b0000; //0
            end
        else if(keyin==4'b1011)
            begin
            bcdz<=4'b0001; //1
            end
        else if(keyin==4'b1101)
            begin
            bcdz<=4'b0010; //2
            end
        else if(keyin==4'b1110)
            begin
            bcdz<=4'b0011; //3
            end
        end
    end
 
always@(bcdz) //Seven Segment Decoder
begin
    case(bcdz)
            0   :   SegOut <=   8'hC0;
            1   :   SegOut <=   8'hF9;
            2   :   SegOut <=   8'hA4;
            3   :   SegOut <=   8'hB0;
            4   :   SegOut <=   8'h99;
            5   :   SegOut <=   8'h92;
            6   :   SegOut <=   8'h82;
            7   :   SegOut <=   8'hF8;
            8   :   SegOut <=   8'h80;
            9   :   SegOut <=   8'h98;
            10    : SegOut <=   8'h88;
            11  :   SegOut <=   8'h83;
            12  :   SegOut <=   8'hC6;
            13  :   SegOut <=   8'hA1;
            14  :   SegOut <=   8'h86;
            15    : SegOut <=   8'h8E;
            default :   SegOut <= 8'hFF;
    endcase
end
endmodule

ads-ee · Jun 28, 2019

cmyang said:
My apologies,I posted in a hurry,forgot to add the annotation,Here I've added some annotates to each part of codes.
I hope these annotates helps you to analyzing to assist me,thanks...

The annotates should be something you add as you write your code not something to add later before posting...adding later usually means they never get added.

cmyang said:
And yes,at this part of circuit design,I'm still quite fuzzy about it,completely lost and have no idea how to continuing,
I can't see the whole big picture,So that's why I'm here to ask a different opinion or approach.

Though,I know I need a state machine to do something about the stored key value,and use state machine to output them on the 7seg,when pressed and scroll it when press next key...
I understand part of the ideas,but just have no idea how to write it/implement it.

This right here is why you don't start coding until you have at a minimum a block diagram of the hardware circuit required to fulfill your required function. This is where you are lost you didn't draw up a block diagram of the design before you started coding. A block diagram and figuring out the architecture is the "design" part of the project...the coding is just translating that design into Verilog which is the easy part, which anyone moderately conversant in Verilog can do.

I already gave you a hint on what you still need to do. You don't really need an FSM to do this just something to detect when the keyin value shows up. Don't know if this involves looking for changes in the code or going from a inactive invalid code to a key press code. You should also determine if the key pad produces clean "codes" with no glitching due to bouncing contacts. If so you'll need to debounce the keyin input (i.e. make sure the value is stable for something like 10ms before saying it has changed/key_pressed).

Welcome to EDAboard.com

Keypad saved number display shift left in Verilog

cmyang

Newbie level 2

KlausST

Advanced Member level 7

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Super Moderator

cmyang

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