Active load differential amplifier design

Hi All,

Can anyone share any document for designing the active load diff amp. I tried designing one with the following specs

VDD = 1.8v, GainBW = 5MHz, Cload = 10pf, ICMR+ = 1.6v, ICMR- = 0.8V, SLEW RATE = 5V/usec, Pdiss <0.3mw.

i started with getting the required tail current source. using slew rate info I_tail = 50uA.

i also calculated the vt and beta values for both pmos and nmos by connecting then in diode connected mos config and making w/l =1.

now from the icmr+ data got the voltage at the mid point(between diode connected pmos load and input nmos) so from there got the required vsd = vsg for pmos. and since the current will be I_tail/2 so calculated the required w/l for the pmoses.

now from the GBW data got the rquired gm data for the input nmos.again since the current itail/2. so got the required w/l.

from ICMR- got the required vdsat for the tail current mos and again calculated the w/l.



please tell whether this is a correct way or did i do some mistake.


i'm facing following issues.

- the tail current source is carrying half of the current even though i'm mirroring 50uA.

- unable to get the required GBW and gain.

so basically my circuit didn't work.Will really appreciate if you guys can tell whether the way i proceeded is wrong(i'm checking my calculations again).

If ny of you can share a basic document for the circuit it'll be of great help.

btw i kept the current mirror dimension same as the tail current even the vgs values are matching. both nmos(input are same) both pmos(active load ) are same.

prateek3790 said:

Hi All,

Can anyone share any document for designing the active load diff amp. I tried designing one with the following specs

VDD = 1.8v, GainBW = 5MHz, Cload = 10pf, ICMR+ = 1.6v, ICMR- = 0.8V, SLEW RATE = 5V/usec, Pdiss <0.3mw.

i started with getting the required tail current source. using slew rate info I_tail = 50uA.

Click to expand...

If I were you, I would begin with the relationship GBW=gm/(2*pi*Cload). You have the value of GBW and the value of Cload. You can get gm from there. Now assume some over-drive. I typically start with 200mV and find the required current. If this current is less than what you would require to meet SR, increase the current and vice versa.

ICMR+ will cause your load pair to go out of saturation. Use that to size the load-pair from the current above.
ICMR- will cause the tail current source to get out of saturation. ICMR_minus - (Vgs,input_pair) > Vdsat, tail current.

ok. so you are saying that instead of fixing the tail current using GBW data, use that to get the gm value for the input nmos. but then i will have 2 unknowns iD and (W/L). do you have any docs or reference regarding one design.

I said something else entirely. Please re-read my answer.

hi i tried as you explained.

gm = 314us, now assumed overdrive of 0.2v and id/2 was 31.4uA.

but from slew rate id needed 25uA. so adjusted overdrive to 0.16v.

used icmr- to get the vds sat for tail and then calculated the w/l.
input nmos w/l got from gm and id/2.

icmr+ got w/l of load.

simulation results

now all were in saturation but my gain is not matching with expected value of gm(gds1 +gds2). where all are simulated values.
can you tell what is wrong ? because all are in sat.


i tried my method also there also same issue all in saturation but gain is not same as simulated values.


my gain should have been 254u/(2.8+2.56)u =~50. but am seeing only 80/20 =~4.

I don't know what simulator you're using but if you can it will be much more helpful if you post a picture of the schematic with the operating point of the transistors annotated.

i'm using synopys custom compiler.

please see the schematc and op analysis.

or if you any design of which you can give me specification of parameters id mentioned.i can try that as well . so if that doesn't match with your results you can get better understanding of my mistakes

When I asked about the operating point, I meant Id, which you show, but also Vov and Vds for the devices and the output DC voltage.
Few things I notice. First, looks like you are simulating the circuit open loop, which means you have to adjust very precisely the input diff voltage, otherwise things shift and there will be no proper operating point.
Also, it looks to me that the polarity of the ac voltages at the inputs is the same, while they have to be opposite in polarity. If they are really the same polarity, means you're simulating the common-mode voltage gain which is supposed to be low.