I have an Avalon MM interface of which I'm the master.
The data that I want to write to the slave is buffered in a FIFO.
To achieve better timing - I want to use a FIFO with a registered output...but it seems impossible with Avalon MM.

This is because the "waitrequest" Avalon MM signal.
Consider the following scenario:
1. The data bus of the master side uses a FIFO with 2 pipeline stages on the output.
2. The user logic sees the waitrequest signal de-asserted so it starts reading data out of the FIFO.
3. Suddenly the waitrequest signal is asserted and because of the pipeline latency - by the time data gets to the slave it's lost.

I know the AXI standard uses "Register Slices" to handle such scenarios - but what about Avalon ?