# NMOS LDO current sense circuit help

1. ## NMOS LDO current sense circuit help

Hi
I am design one NMOS LDO with current limit function.The dropout of NMOS is 200mV.The supply is set 5.2V,the out is 5V. How can i sense the output current of ldo.
Thanks !

2. ## Re: NMOS LDO current sense circuit help

Hi,

We can help you, but we wonīt do the design for you.
So:
* show us your idea (even a hand drawn sketch will do)
* I assume you already did some internet search. What are the results? Whatīmeets your requirements? What did not meet your requirements?

Did you notice? You talk about "current sense" but did not post any information about the expected current.

Nor did you give any requirements about your current sensing: Analog, digital, bandwidth, resolution, sampling rate, precision, accuracy...

Klaus

3. ## Re: NMOS LDO current sense circuit help

first thank you very much
I am designing a NMOS LDO with current limit function. The shematic is

because use current mirror ,the current limit accuracy is poor. So i hope to get some advice and idea.
The requirement for the ldo is dropout=200mV， load current 0~1A. Under this requirement , there is any other idea.
Thanks

4. ## Re: NMOS LDO current sense circuit help

Hi,

The first thing that comes into my mind is to use a resistor to sense the current. This gives a voltage that is proportional to the current. Use this voltage as current measurement signal.
I donīt see all this in your circuit.

Klaus

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5. ## Re: NMOS LDO current sense circuit help

Hi,
Yes, I use the idea which I multi R. First ,I mirror the load current with a current mirror (1000:1). Then the current multi with the resistor which show in the lower right.
Thanks

6. ## Re: NMOS LDO current sense circuit help

Originally Posted by yucw
Hi
I am design one NMOS LDO with current limit function.The dropout of NMOS is 200mV.The supply is set 5.2V,the out is 5V. How can i sense the output current of ldo.
Thanks !
The simplest way I know is use "current mirror", so it will not make drop voltage too high.

If you want design from IC component, the simple way is using In-amp or Opam with VCC higher 2V of DC line voltage.

7. ## Re: NMOS LDO current sense circuit help

Hi,

you are doing discrete design or IC design?
.. would be good to know. (until post#5 I thought about discrete design)

Klaus

8. ## Re: NMOS LDO current sense circuit help

Hi,

Thanks for you reply.

Sorry,this is IC design.
I can not see the schematic.

Thanks

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9. ## Re: NMOS LDO current sense circuit help

I think you have too much gain in the current control loop, and if the speed of the control loop is comparable with the settling speed of the main LDO feedback system, than it can cause unstability or ringing. What do you mean on that your control accuracy is poor? How much accuracy you need? In percentage. And how much is the target current limit?

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10. ## Re: NMOS LDO current sense circuit help

You might use the metal run from pass FET source to

It will be difficult or impossible to get a good current mirror
fidelity with so little headroom, and your 5.2V in, 5.0V out
setup really would prefer a PMOS pass device (unless you
have an AUX supply that is well higher than VIN, for pass
FET gate overdrive range.

A NMOS current mirror that pulls on a VIN-referred burden
resistor for some up-front gain, and a subsequent active
gain / compare function, could give you a "good enough"
current limit. This depends on expectations and who gets
to set them. Does it have to be fast, have to be stable,
have to do something more complex like foldback current
profile rather than plateau, etc.

11. ## Re: NMOS LDO current sense circuit help

Originally Posted by frankrose
I think you have too much gain in the current control loop, and if the speed of the control loop is comparable with the settling speed of the main LDO feedback system, than it can cause unstability or ringing. What do you mean on that your control accuracy is poor? How much accuracy you need? In percentage. And how much is the target current limit?
Yes, you are right. The current control loop has too much gain and the speed is same as the main LDO.This is a problem that I have no idea to deal it.The ideal current limit vaule is set by VREF/R, the current limit circuit is triggered while the load current did not reach the set value. There is 20 percentage error.

- - - Updated - - -

Originally Posted by dick_freebird
You might use the metal run from pass FET source to

It will be difficult or impossible to get a good current mirror
fidelity with so little headroom, and your 5.2V in, 5.0V out
setup really would prefer a PMOS pass device (unless you
have an AUX supply that is well higher than VIN, for pass
FET gate overdrive range.

A NMOS current mirror that pulls on a VIN-referred burden
resistor for some up-front gain, and a subsequent active
gain / compare function, could give you a "good enough"
current limit. This depends on expectations and who gets
to set them. Does it have to be fast, have to be stable,
have to do something more complex like foldback current
profile rather than plateau, etc.
The metal sense resistor is a good scheme for some application. Because the metal resistor process error is about ą20 percentage , so i have not use this scheme. For big load current, the pmos size will be very impressive， so i use the NMOS pass device. Normally, there is a charge pump to drive the pss FET gate.

12. ## Re: NMOS LDO current sense circuit help

You might compare PMOS pass FET to {NMOS pass FET
plus charge pump actives and caps} - "solution size", not
just the pass FETs.

Current sense accuracy matters little in current mode
control, the voltage loop will swallow any minor errors.

The question of how accurate a short circuit current
limit needs to be, and who says so, remains.

13. ## Re: NMOS LDO current sense circuit help

Hi

If you design from IC solution, I suggest you use complete solution as LTC (ADI) with Surge-stopper, other supplier call it is e-fuse.

It is clear that almost LDO in the market claim that it have current limit or short circuit function. But, in fact, when issue happen, LDO still spoiled. So, that protect function is no meaning.

We come back your purpose why you need current sense for LDO ?
With my experiment, it will use for 02 cases: monitor energy & protection.

If you use for monitor, you can use some specific IC, so it is more accuracy and reduce developing time. -> Used Instrument amplifier, like INA193 (for cheap), or LTC6115.

If you use for protection, you should separate the function. As the #9 said, it is un-wanted case like ringing, ad more noise to output. That mean makes LDO operate malfunction.
The most purpose of LDO is keep constant output voltage and reject noise from input power.
The proposal is Protector stand in front of which need protection. Input -> Surge stopper -> LDO/Switching -> Load.
Protector need separate from main operating object to warranty the reliability of system. Monitor system vs actuator system is independent.

You can take a look at surge stopper LT4356, it will help you multiple protect function:
limit inrush current, over/under voltage, setting time of over current (capacitor load), over voltage, reverse input voltage. And it use N-fet for lower Rdson, cost, popular, ...

My friend use LT4356, LT4380 for motor driver protect, RF power amplifier (PA) and feedback it is helpful and avoid spoiling expensive component.

14. ## Re: NMOS LDO current sense circuit help

Originally Posted by Taihung
Hi

If you design from IC solution, I suggest you use complete solution as LTC (ADI) with Surge-stopper, other supplier call it is e-fuse.

It is clear that almost LDO in the market claim that it have current limit or short circuit function. But, in fact, when issue happen, LDO still spoiled. So, that protect function is no meaning.

We come back your purpose why you need current sense for LDO ?
With my experiment, it will use for 02 cases: monitor energy & protection.

If you use for monitor, you can use some specific IC, so it is more accuracy and reduce developing time. -> Used Instrument amplifier, like INA193 (for cheap), or LTC6115.

If you use for protection, you should separate the function. As the #9 said, it is un-wanted case like ringing, ad more noise to output. That mean makes LDO operate malfunction.
The most purpose of LDO is keep constant output voltage and reject noise from input power.
The proposal is Protector stand in front of which need protection. Input -> Surge stopper -> LDO/Switching -> Load.
Protector need separate from main operating object to warranty the reliability of system. Monitor system vs actuator system is independent.

You can take a look at surge stopper LT4356, it will help you multiple protect function:
limit inrush current, over/under voltage, setting time of over current (capacitor load), over voltage, reverse input voltage. And it use N-fet for lower Rdson, cost, popular, ...

My friend use LT4356, LT4380 for motor driver protect, RF power amplifier (PA) and feedback it is helpful and avoid spoiling expensive component.
Thanks for your advice. I am designing a chip and the ldo is a moudle in it.

15. ## Re: NMOS LDO current sense circuit help

I think you could try these things:
a, add calibration to balance the error of the current mirror. It is reliable, many ways you can implement it, some example:
- analog: potentiometer instead of R
- digital: add a DAC circuit to generate 600mV comparator reference voltage, possibly low resolution is enough to reach a 1-5% percent error. Search for R-string DAC, it is small.
b, instead of the bottom comparator use an OTA with a "huge" capacitor on its output. It will slow down the current control loop.
c, to reduce the current control loop gain add source degeneration to the bottom transistor's source. A resistor or a current source maybe.

16. ## Re: NMOS LDO current sense circuit help

So, given that this is an internal application, who is making
the current sense a requirement, and what are the required
attributes?

If the output is not exposed, or only exposed to a local
decoupling pin and no external load that could go shorted,
what is then the value of current limit? Presumably if the
on-chip LDO is presented a shorted load, it's because
there's an on-chip short (so already hosed)?

Are you building a LDO which can survive a "dead client"?
If so, what's the value proposition?

17. ## Re: NMOS LDO current sense circuit help

Originally Posted by dick_freebird
So, given that this is an internal application, who is making
the current sense a requirement, and what are the required
attributes?

If the output is not exposed, or only exposed to a local
decoupling pin and no external load that could go shorted,
what is then the value of current limit? Presumably if the
on-chip LDO is presented a shorted load, it's because
there's an on-chip short (so already hosed)?

Are you building a LDO which can survive a "dead client"?
If so, what's the value proposition?
The LDO can be used to charge some device, such as li-ion. The market havs many ldo chips with current limit fuction.

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18. ## Re: NMOS LDO current sense circuit help

Originally Posted by frankrose
I think you could try these things:
a, add calibration to balance the error of the current mirror. It is reliable, many ways you can implement it, some example:
- analog: potentiometer instead of R
- digital: add a DAC circuit to generate 600mV comparator reference voltage, possibly low resolution is enough to reach a 1-5% percent error. Search for R-string DAC, it is small.
b, instead of the bottom comparator use an OTA with a "huge" capacitor on its output. It will slow down the current control loop.
c, to reduce the current control loop gain add source degeneration to the bottom transistor's source. A resistor or a current source maybe.
During the simulation, the current control loop gain is so high to influnence main loop output. Reduce the current loop gain should be done.

19. ## Re: NMOS LDO current sense circuit help

During the simulation, the current control loop gain is so high to influnence main loop output. Reduce the current loop gain should be done.
Sounds like a cryptic description of instable current control loop. That's expectable, you want to analyze loop phase margin and provide approriate frequency compensation. Hint: loop stability depends on the load impedance.

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