In the timing libs, I can find the "output" ports, see their "Related_pin", and report delay calculation from related_pin to output_port. However, how can I do this for all output ports and their related pins automatically?

Basically I receive a timing lib from a designer that I know nothing about (Except the lib itself) of a single cell, and I'm trying to find the delays from inputs to outputs, for whatever paths are available from each input to each output.

The other questio is, how can i find which paths are available?

Thank you