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  1. #1
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    vcom-1263 Error with generate and component instantiation

    First see https://stackoverflow.com/questions/...-applies-to-no

    Now instead of including the

    for all : x use entity lib.x within the generate statement block_declarative_part

    Is it possible to have config information in the main architecture block declarative part but include the hierarchy.

    for all : generate_label.x use entity lib.x

    The above didn't work for me. I was curious if people knew an answer, or does the limitation of the language and tool mean we are resigned to co-locate the config info.

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  2. #2
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    Re: vcom-1263 Error with generate and component instantiation

    I dont know the answer to this specifically, because I never use configurations (and Ive never seen them used or needed them).
    Unless you have multiple architectures, they're pretty useless. Even if you have multiple architectures, using direct instantiation you can specify the architecture and then use generics/generates to instantiate different architectures. (And again, Ive never written multiple architectures)

    Can I ask why you're using configurations?


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  3. #3
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    Re: vcom-1263 Error with generate and component instantiation

    Can I ask why you're using configurations?
    Like many things in life, I'm force to do it through circumstance.

    The legacy code that I've inherited is like the stackoverflow question.

    They used for all statements in the wrong level of scope.

    There are instances, where different files have the same filename. This is because over the years multiple individual asic designs were merged into a bigger fpga. Therefore functionx.top would be different to functiony.top however they both are top.vhd, just located in different directory structures.

    I've already replaced the configurationally part to the generate statement block declarative part and this has removed warnings.

    Regards.



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