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    Mixed Signal IC Grounds

    Hi guys!
    I am currently working on a mixed signal project in research. I am at the beginning of my PhD and am working on an institute where a lot of analog knowhow is present. but only minimal digital. This is my topic.
    While I am able to create digital design blocks in innovus, the know how how to implement everything is a little lacking. So my question is:

    How to handle ground and vdd connections?
    What I have thought was to have the digital VSS net, the analog VSS net and the VSS net for IOs....those will be only connected on PCB quite next to the ASIC. I think this is needed to not eintroduce the ground bounce created from the digital circuit to the analog, and not to connect the groudn bounce from the IO drivers to anything at all...
    VDD nets are also seperate, I plan to seperate them on the PCB as well.

    How to do it properly?

    THank you a lot and have a nice day!
    Alex

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    Re: Mixed Signal IC Grounds

    I think you are on the right track.
    Also, digital is only a special case of analog, so don't panic. Just understand that digital signals jump around a lot and are hence high frequency noisy and sometimes power transient sources.

    If you go very high speed digital, then there are other problems of course. But digital up to around 50-100 Mhz should be ok.



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    Re: Mixed Signal IC Grounds

    Thank you for your answer!

    What other problems arise with higher frequency? I am planing to clock up to 500 MHz.

    Thank you!



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    Re: Mixed Signal IC Grounds

    Don't forget that your planning still has to respect whatever constraints that come with the package and the IO cells. I have often seen packages and IO rings that short all grounds together, so it becomes pointless to separate VSS at board level. It can be expensive to have package with dual VSS planes. It can be possible to separate the VSS on the rings with breaker cells but that requires some finesse.
    Really, I am not Sam.


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    Re: Mixed Signal IC Grounds

    Thank you for that though, I haven't thought about that yet since we are doing research and our dies are glued to pcb's with a conductive glue and bonded straigth to the PCB.



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    Re: Mixed Signal IC Grounds

    1. Separate analog and digital supplies and grounds. I believe you are already doing it.
    2. Place separation between analog and digital blocks and fill it with ground cells. Substrate noise is also an issue that cannot be ignored. Because you are in research, be generous with that.
    3. Large decoupling capacitors CLOSE to the blocks. By the way too much decoupling capacitors can also result in oscillations inside the chip. So its a good idea to de-Q the decoupling capacitors by using MOS transistors.


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    Re: Mixed Signal IC Grounds

    Quote Originally Posted by vivekroy View Post
    1. Separate analog and digital supplies and grounds. I believe you are already doing it.
    2. Place separation between analog and digital blocks and fill it with ground cells. Substrate noise is also an issue that cannot be ignored. Because you are in research, be generous with that.
    3. Large decoupling capacitors CLOSE to the blocks. By the way too much decoupling capacitors can also result in oscillations inside the chip. So its a good idea to de-Q the decoupling capacitors by using MOS transistors.
    For 2:
    We are mainly working on optoelectronics, so any circuits has to be isolated from substrate anyhow (using a deep, low doped N-Well). Substrate level is around 25V lower than where the circuits operate. I know there is some coupling of substrate noise, so every block is enclosed with substate ties.

    3:
    Since power consumption is not a major concern, I plan my digital blocks only with a density of 80% and fill the remainder with digitcal decap cells (moscaps). All the analog blocks get MIM caps. Do you think that is fine? What do you mean with "So its a good idea to de-Q the decoupling capacitors by using MOS transistors. "?

    Thank you!



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    Re: Mixed Signal IC Grounds

    MIM caps are high Q capacitors. The inductance in the supply path (trace inductance) + decoupling capacitors can form a series LC tank. To make sure that you don't end up with large supply oscillations, you need to use a low Q cap.
    Plus, doesn't MOS capacitors have a higher density than MIM caps?



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