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Design compiler synthesis

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vyella1

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Hello Forum,
I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC. Accidentally I turned on a pipeline stage in different path (critical path and this path are not related at all) and it fixed the timing violation. Is it normal to see such synthesis behavior? I am trying to understand how it fixed the timing violation.
 

Hello Forum,
I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC. Accidentally I turned on a pipeline stage in different path (critical path and this path are not related at all) and it fixed the timing violation. Is it normal to see such synthesis behavior? I am trying to understand how it fixed the timing violation.

I assume some form of retiming took place.
 

Thank you for responding Really, I am not Sam.
Even I thought the same and I checked the log file, the retiming option is not turned on
 

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