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[SOLVED] How to load an already compiled design in Design Compiler?

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asic_architect

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Hello,

I have already compiled a large design and wrote out .ddc. and exited DC. I am looking to do some optimizations on the same design. If I load that .ddc, I get different QoR than the original. I am just loading the .ddc. What am I doing wrong? Is there any other file I should load?

Tks
 

asic_architect said:
Hello,

I have already compiled a large design and wrote out .ddc. and exited DC. I am looking to do some optimizations on the same design. If I load that .ddc, I get different QoR than the original. I am just loading the .ddc. What am I doing wrong? Is there any other file I should load?

Tks
Click to expand...

you need to reload the netlist, any constraints, corners, and all libraries.
 

Shouldn't the constraints be contained within the ddc? I think most are. But it's possible that the timing_derate contraints are not contained in the ddc. If anyone can confirm this please comment. I'm running experiments now.
 

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