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[SOLVED] verilog set parameter to a module

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Hi,
I came across following generated code from vivado:

Code Verilog - [expand]
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(* EXAMPLE_SIMULATION = "1" *) 
  (* SIM_SPEEDUP = "FALSE" *) 
  some_ip some_ip_inst(
 .a(a),
.b(b)
 );




I know to set parameter inside module we use this way:
some_ip
Code Verilog - [expand]
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#(
        .EXAMPLE_SIMULATION  (1), 
        .SIM_SPEEDUP ("FALSE")
       )
    some_ip_inst(
 .a(a),
.b(b)
 );


or use defparam to overreide :
defparam hierarchical_path = paratemter value;


but I didn't understand which kind of syntax is this?
Code Verilog - [expand]
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(* EXAMPLE_SIMULATION = "1" *) 
  (* SIM_SPEEDUP = "FALSE" *)

can anybody explain it?
 
Last edited by a moderator:

The (* some_attribute = some_value *) are for synthesis attributes. Though in this case the attributes don't look like synthesis attributes, they must be custom attributes. They certainly don't show up as attributes in the synthesis guide.
 

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