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  1. #1
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    Synposys Tcyc not observed

    I'm new to Synposys DC and I'm having trouble with timing analysis. Basically, I've got memories generated through TSMC's mc2-eu tool. Looking at the output .lib and simulation Verilog, they seem to be reasonable blackbox units. However, when I instantiate them and define/constrain a clock, it appears as though Synopsys is only concerned with the clk->Q time and disregards the tcyc - the minimum clock cycle time listed in the memory's datasheet.

    For example, the script below should violate timing when the tcyc for the memory is greater than 0.5ns. However, Synopsys happily passes this through, only quoting the clk->Q path when looking at the timing report. What am I doing wrong?


    Code:
    set target_library {pointToLogicLibrary.db}
    set additional_link_lib_files {pointToMemoryLibrary.db }
    set link_library "* $additional_link_lib_files $target_library"
    
    read_file -format sverilog memoryInstantiation.sv
    set current_design topLevelDesign
    
    create_clock -period 0.5 -name clk clk
    set_max_area 0 
    
    compile_ultra
    report_timing -transition_time -nets -attributes -nosplit

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  2. #2
    Newbie level 4
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    Re: Synposys Tcyc not observed

    Looking at the source .lib in more detail, I guess my question is why doesn't Design Compiler pick up and use the "timing_type: minimum_period" constraint? I've tried modifying the "when" and "sdf_cond" parameters to see if it would help the behavior of dc_shell, but this doesn't seem to work either.

    Code:
            timing () {
                timing_type : minimum_period ;
                related_pin : "CLKW" ;
                /*when : "!WEB" ;*/
                /*sdf_cond : "!WEB" ;*/
                rise_constraint ( "clktran_constraint_template" ) {
                    values ( "0.615669, 0.622012, 0.627074, 0.634192, 0.874000" ) ;
                }
                fall_constraint ( "clktran_constraint_template" ) {
                    values ( "0.615669, 0.622012, 0.627074, 0.634192, 0.874000" ) ;
                }
            }
    - - - Updated - - -

    I figured this out. Design Compiler evidently considers min_pulse_width and min_period constraints separately from setup and hold times. To see these violations you need to add the "report_constraint -min_pulse_width -min_period" command to the dc_shell script.



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