blindscience
Newbie level 4
I'm new to Synposys DC and I'm having trouble with timing analysis. Basically, I've got memories generated through TSMC's mc2-eu tool. Looking at the output .lib and simulation Verilog, they seem to be reasonable blackbox units. However, when I instantiate them and define/constrain a clock, it appears as though Synopsys is only concerned with the clk->Q time and disregards the tcyc - the minimum clock cycle time listed in the memory's datasheet.
For example, the script below should violate timing when the tcyc for the memory is greater than 0.5ns. However, Synopsys happily passes this through, only quoting the clk->Q path when looking at the timing report. What am I doing wrong?
For example, the script below should violate timing when the tcyc for the memory is greater than 0.5ns. However, Synopsys happily passes this through, only quoting the clk->Q path when looking at the timing report. What am I doing wrong?
Code:
set target_library {pointToLogicLibrary.db}
set additional_link_lib_files {pointToMemoryLibrary.db }
set link_library "* $additional_link_lib_files $target_library"
read_file -format sverilog memoryInstantiation.sv
set current_design topLevelDesign
create_clock -period 0.5 -name clk clk
set_max_area 0
compile_ultra
report_timing -transition_time -nets -attributes -nosplit