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Loop Compensation Characteristics with Degraded parts in Boost PFC.

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Hayagriv

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Dear Edaboard,

I am a NEW hire in our company and I am trying to understand the Analog PFC in the design.

In a PFC, the most critical components are MOSFET, DIODE and the E-cap which can degrade over a period of time.

E-cap Degradation, implies either ESR value increases or Capacitance decreases. Can anyone let me know how this affects both the loop (Voltage and Current loop) compensation of the circuit.

Also, MOSFET and Diode degradation, mainly because of thermal heating and it may result in higher loss in the components as far as I know. Can anyone please let me know if there are any parameters in these components change due to degradation..?

If so, how the degradation of MOSFET and Diode affects the loop compensation.?

Please help me to understand the topic in detail.

Thanks in advance for your help.

Regards,
Hayagrivan
 

over time the E cap will lose capacitance and the ESR will go up - depending on how hard it is used ( rms current ) losing capacitance means the 100/120 Hz ripple will go up - but the o/p will respond faster - there is no way to allow for this in the control loop successfully when you are designing for "as new" conditions ...

If the ESR rises the cap will heat and it will die faster - there is no control loop remedy for this either ....
 

My question was what is the effect of control loop with the degradation of E-cap. I know the loop will get affected, but I need to know how.?

Also, need to know about the degrading parameters of Diode and MOSFET.
 

Easy peasy has answered your question from a designers/instrument manufacturers perspective.

To investigate the detail effects, perform a simulation. My assumption is this: If your voltage control loop is compensated reasonably, stability margin will rather increase than decrease with capacitor degradation. You'll nevertheless observe unwanted effects not related to loop compensation. Current control loop (usually peak current control) won't be affected at all.

You should also consider that the useful PFC voltage loop corner frequency is usually restricted by acceptable harmonic current rather than stability margin.
 

You may run feedback loop measurements...then imitate a degraded ecap by putting in a smaller one with a resistor in series ...then repeat and see how it goes for phase and gain margin....

...but of course, it wont be quite perfect because the esr is a frequency dependent resistance , but at and around the crossover frequency, the esr will be pretty much the same.

https://www.youtube.com/watch?v=1JHreLvaDwo

- - - Updated - - -

but by the time an ecap at the output of a boost pfc gets so degraded that it significantly affects the power factor, then i reckon the ecap itself may just blow up.
 

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