adrianf0
Newbie level 3
Hi,
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem?
I know that something like:
could work, but according to my knowledge, the is_x function may have a problem with synthesis.
Another option would be to write a process:
However, I am worried that the synthesis tool may have an issue to extract a proper and simple mux from this description.
Is there any more straightforward description? I am using VHDL 2008.
Regards,
Adrian
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem?
I know that something like:
Code:
output <= (others => '-') when is_x(address) else registers(to_integer(address));
Another option would be to write a process:
Code:
mux: process(all)
begin
output <= (others => '-');
for i in registers'range loop
if address = to_unsgined(i, address'range) then
output <= registers(i);
end if;
end loop;
end process;
Is there any more straightforward description? I am using VHDL 2008.
Regards,
Adrian