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    Is it possible to assign a value to a signal in a systemverilog assertion?

    hi,

    I have two sequences, s1 and s2. I have a property that checks these two sequences.
    for example,

    Code:
    sequence s1 
    req ##3 gnt;
    endseqence
    
    sequence s2
    ack;
    endsequence
    Now I make use of a property for an assertion to check these two sequences.

    Code:
    property p1;
    @(posedge clk) disable iff(reset)
    s1 |-> s2;
    endproperty
    
    assert property (p1) else $warning("Assertion failed");

    Once the property has been asserted successfully, is there a way where I can trigger a signal (say X) HIGH? I want it to trigger HIGH only when the property has been successfully asserted during the rest of the time, I want it to be LOW.

    Any suggestions would be of great help, thank you.

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  2. #2
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    kripacharya's Avatar
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    Re: Is it possible to assign a value to a signal in a systemverilog assertion?

    Surely there exists the equivalent of an IF-THEN-ELSE construct in whatever language you ainre using? That's programming 101.

    I notice an 'iff' keyword.? ?



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  3. #3
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    Re: Is it possible to assign a value to a signal in a systemverilog assertion?

    Quote Originally Posted by iammedjay View Post
    hi,

    I have two sequences, s1 and s2. I have a property that checks these two sequences.
    for example,

    Code:
    sequence s1 
    req ##3 gnt;
    endseqence
    
    sequence s2
    ack;
    endsequence
    Now I make use of a property for an assertion to check these two sequences.

    Code:
    property p1;
    @(posedge clk) disable iff(reset)
    s1 |-> s2;
    endproperty
    
    assert property (p1) else $warning("Assertion failed");

    Once the property has been asserted successfully, is there a way where I can trigger a signal (say X) HIGH? I want it to trigger HIGH only when the property has been successfully asserted during the rest of the time, I want it to be LOW.

    Any suggestions would be of great help, thank you.
    this is counter intuitive. assertions are a verification artifact, they should not interfere with the design, nor generate any signals on demand.

    - - - Updated - - -

    Quote Originally Posted by kripacharya View Post
    Surely there exists the equivalent of an IF-THEN-ELSE construct in whatever language you ainre using? That's programming 101.

    I notice an 'iff' keyword.? ?
    you missed the point completely.
    Really, I am not Sam.



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  4. #4
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    Re: Is it possible to assign a value to a signal in a systemverilog assertion?

    Quote Originally Posted by kripacharya View Post
    I notice an 'iff' keyword.?
    This is a regular statement on this language.
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    Part of the world that you live in, You are the part that you're giving ( Renaissance )



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