CMRR is less than the DC differential gain

1. CMRR is less than the DC differential gain

Hello friends,

I am simulating the CMRR of my amplifier, I am getting the CMRR = 80 dB at DC frequency while the DC differential gain is 103 dB. My amplifier is fully differential amplifier,

How it is possible that CMRR is less than the differential gain ??

Note.. this is the Postlayout simulation results

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2. Re: CMRR is less than the DC differential gain

Because the DC diff gain is what's giving the CMRR and there
is always a "hidden tax" - like nodes with positive common
mode gain, which have to be overcome.

If you take the open loop diff gain and the open loop CMRR
("gain") and scrub them together, do you get something more
like the simulated closed loop CMRR?

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3. Re: CMRR is less than the DC differential gain

2 possible reasons:
a, you have big common mode gain because CMRR(dB) = Ad(dB) - Acm(dB)
b, you do something wrong
Check signs, expressions in calculator, the testbench itself.

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4. Re: CMRR is less than the DC differential gain

Dear friends,

I have simulated the circuit with schematic view and give a reasonable value of CMRR.

The problem is only at post layout simulation. As Frankrose has mentioned, I have a common mode gain of 23 dB.

I don't know why I have a big common mode gain after the layout

Does it mean that my design fails and I can not submit it when CMRR is less than the differential gain ??

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by the way I am simulating the CMRR by two methods, from the closed and open loop configuration and having the same result

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is it possible even to have such high common mode gain ?

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5. Re: CMRR is less than the DC differential gain

Transient simulations giving similar results? How you generates post-layout netlist?

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6. Re: CMRR is less than the DC differential gain

Originally Posted by Dominik Przyborowski
Transient simulations giving similar results? How you generates post-layout netlist?
Dear dominik

In the transient simulation is giving near perfect results, however it is depending on the ampliftude of the applied signal, it is degrading as the input amplitude increasing.

I am running the QRC extractor from cadence to generate the circuit netlist with the parastatic cap and res

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I am using this simulation setup in Fig.3

https://www.analog.com/media/en/trai...als/MT-042.pdf

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I am thinking that it is wrong to apply high amplitude common mode voltage in the transient simulation,,, the common mode voltage in reality is comparable to the common noise level which should be maximum it terms of several tens mV... if it is like that then my transient simulation is

7. Re: CMRR is less than the DC differential gain

In line with the fully differential amplifier threads you have posted during the last months, I assume that your amplifier will be operated with external feedback and the said "DC differential gain" is just an open loop parameter. The ratio of CMRR to open loop gain isn't of much significance then.

CMRR requirements are application specific, particularly CMRR at the higher end of the intended frequency range is usually a critical parameter if an amplifier is e.g. wanted to reject common mode signals.

Similarly, I don't generally agree that large signal common mode rejection is irrelevant, it may be of much interest depending on the application. But it's no parameter found in standard specifications.

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8. Re: CMRR is less than the DC differential gain

Dear Fvm
Dear friends

in the last months when I was used to ask about the CMRR, I was just doing the schematic design, at that time I had very big value, then you told me that is ok because my amplifier in the schematic looks very symmetrical which will not be the case after the layout,,, the thing it should be dropped but not as bad as I am getting

How much you suggest me a voltage level of common mode voltage to simulate it in transient ?

and please you didn't tell me if it can happen to see an amplifier with CMRR less than the differential DC gain

9. Re: CMRR is less than the DC differential gain

Compare the current consumption and dc levels between schematic and extract (I suppose you are using OA views, nor spf netlist - correct me if my assumption is wrong).
Generate device only extraction and compare the netlists (using for example tkdiff). Check whether mosfet are netlisted with the same parameters (I don't remember whether C35 pdk provides any LDE).
Simulate 4 cases - schematic, extract no parasitic, c only and RC.

If you are using Assura tool (especially version 4.1) to perform LVS and you will see discrepancy in DC operating points, it can be possible that layout is not matched with schematic even with LVS passes by Assura.

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10. Re: CMRR is less than the DC differential gain

Originally Posted by Dominik Przyborowski
Compare the current consumption and dc levels between schematic and extract (I suppose you are using OA views, nor spf netlist - correct me if my assumption is wrong).
Generate device only extraction and compare the netlists (using for example tkdiff). Check whether mosfet are netlisted with the same parameters (I don't remember whether C35 pdk provides any LDE).
Simulate 4 cases - schematic, extract no parasitic, c only and RC.

If you are using Assura tool (especially version 4.1) to perform LVS and you will see discrepancy in DC operating points, it can be possible that layout is not matched with schematic even with LVS passes by Assura.
Dear Dominik

I have noticed in some cases that netlist from schematic is different from the netlist of layout, like changing the drain source positions,, how can I correct it for the LVS i mean how can I correct the error in the generated netlist, I am using Assura

11. Re: CMRR is less than the DC differential gain

Dc operating points for schematic and extracted views. What they are?

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