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How to clock gate in hierarchy?

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DimitrisStathis

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Hi,

I am trying to clock gate a part of my design with one enable signal. It seems logical to me that instead of using the enable signal to each register inside the modules and sub-modules, it would be better to directly gate the clock high in the hierarchy.
I would like to use the special clock gating cell from the std cell library and not the generic latches and gates. Is there a way to infer the clock gating to the synthesis tools?
Is there something like the synopsys DW or gtech library, for example, that can infer clock gating cells?

Best Regards,
Dimitrios
 

Logic synthesis tools and CTS are able to handle that automatically for you. Do not code or instantiate clock gating by hand.
 

Hello ThisIsNotSam,

Thank you for your reply.

I know that Synthesis tools can infer the clock gating in the registers, when the registers are using enable signals. But what I want to do is to completely enable/disable a big part of my design hierarchy with a single enable signal. I seems like a bad idea to push the signal through the whole hierarchy just to allow the synthesis tool to automatically infer the clock gating. Since I know that I want to gate the clock for that part of my design I think there should be a clean way to do that on the top.

Best Regards
Dimitrios
 

DimitrisStathis said:
Hello ThisIsNotSam,

Thank you for your reply.

I know that Synthesis tools can infer the clock gating in the registers, when the registers are using enable signals. But what I want to do is to completely enable/disable a big part of my design hierarchy with a single enable signal. I seems like a bad idea to push the signal through the whole hierarchy just to allow the synthesis tool to automatically infer the clock gating. Since I know that I want to gate the clock for that part of my design I think there should be a clean way to do that on the top.

Best Regards
Dimitrios
Click to expand...

Sure, you can try to play with the CTS at block level, or even do some PSO if the block is really not going to operate for a long period of time. Can it be done? Absolutely. Especially if you have a partitioned design, very easily. Just don't expect a miraculous energy saving, the tools are already quite good at this sort of thing.
 

ThisIsNotSam said:
Sure, you can try to play with the CTS at block level, or even do some PSO if the block is really not going to operate for a long period of time. Can it be done? Absolutely. Especially if you have a partitioned design, very easily. Just don't expect a miraculous energy saving, the tools are already quite good at this sort of thing.
Click to expand...

Thanks for the reply,
My question is how to infer a clock gating cell from the std cell library. I know that I can describe in rtl a latch base clock gating cell, but in that case the synthesizer will use the generic latch and gates from the library instead of the special clock gating cells that are included in the library.
Is there a way to tell the synthesis tool to use the special clock gate cell and consider my cell as part of the clock tree? So that it can select the cell with the appropriate drive strength etc.

Best Regards,

Dimitrios
 

Just instantiate the cell you want by hand. Tell synthesis not to touch it.
 

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