# stretching the 0 pulse of a digital output with a certain T

1. ## stretching the 0 pulse of a digital output with a certain T

Hello, i have a digital output with varying pulse sizes and i want to stretch the 0 output for a constant T+ 0 pulse time. I have tried using a monostable multivibrator with a NAND gate but the problem i got is that the length of the pulse remains constant, which could be a problem if the pulse width is greater than the multivibrator output so how to add this time constant to the original pulse width instead?

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here's an image of the desired output

2. ## Re: stretching the 0 pulse of a digital output with a certain T

Hi,

Specify the timing. Is it picoseconds or hours?

What supply voltage and what logic family?

Klaus

3. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by KlausST
Hi,

Specify the timing. Is it picoseconds or hours?

What supply voltage and what logic family?

Klaus
Timing is about 50-100ms. Supply voltage 3.3V and it's an integrated circuit

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4. ## Re: stretching the 0 pulse of a digital output with a certain T

100ms is a lot for an IC. If you have a clock, use a counter for the timing.

5. ## Re: stretching the 0 pulse of a digital output with a certain T

the RC could be added outside or i can just reduce the time

6. ## Re: stretching the 0 pulse of a digital output with a certain T

The problem with the circuit you propose (monostable and NAND gate) is the NAND gate. You want a '0' output if EITHER the monostable is low (in the case of the pulse being shorter than the monostable period) OR the pulse is low (in the case of the pulse being longer than the monostable period).
Therefore the output should be '1' only when BOTH the input line and the monostable are high - so you want an AND gate.
(This assumes that the \Q\ output of the monostable is being used - that's the one that is normally high and low when the monostable is triggered.)
Drawing out the timing diagram of the situation when the pulse is longer than the monostable period and putting that with the one you drew in the first post would show you the solution.
Susan

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7. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by Aussie Susan
The problem with the circuit you propose (monostable and NAND gate) is the NAND gate. You want a '0' output if EITHER the monostable is low (in the case of the pulse being shorter than the monostable period) OR the pulse is low (in the case of the pulse being longer than the monostable period).
Therefore the output should be '1' only when BOTH the input line and the monostable are high - so you want an AND gate.
(This assumes that the \Q\ output of the monostable is being used - that's the one that is normally high and low when the monostable is triggered.)
Drawing out the timing diagram of the situation when the pulse is longer than the monostable period and putting that with the one you drew in the first post would show you the solution.
Susan
ok is there any possible way to stretch it for around 100ns digitally without using the RC?

8. ## Re: stretching the 0 pulse of a digital output with a certain T

Hi,

ok is there any possible way to stretch it for around 100ns digitally without using the RC?
You did not react on this suggestion...

Klaus

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9. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by sutapanaki
100ms is a lot for an IC. If you have a clock, use a counter for the timing.
implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?

10. ## Re: stretching the 0 pulse of a digital output with a certain T

I'm not sure what we are currently talking about because the original 100 ms delay shrunk to 100 ns in the meantime. There's a certain state of the art for reset generators, usual delays are in a several 10 to several 100 ms range. They are implemented as digital timers with e.g. high kHz oscillator to save chip area. Purely analog implementations with pF capacitor and pA current source would be possible nevertheless, probably less accurate.

implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?
Why particularly?

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An analog reset timer with external timing capacitor http://www.ti.com/lit/gpn/tps3895

11. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by FvM
I'm not sure what we are currently talking about because the original 100 ms delay shrunk to 100 ns in the meantime. There's a certain state of the art for reset generators, usual delays are in a several 10 to several 100 ms range. They are implemented as digital timers with e.g. high kHz oscillator to save chip area. Purely analog implementations with pF capacitor and pA current source would be possible nevertheless, probably less accurate.

Why particularly?

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An analog reset timer with external timing capacitor http://www.ti.com/lit/gpn/tps3895
i have a 50MHz clock provided so i was thinking about delaying it digitally without using any capacitors as another solution for at least 2 cycles (40ns) by using a Dflipflop as a frequency divider but this will affect both pulses, which is not desired. The provided gates in the technology are the primitive gates so if i want to implement more complicated gates i have to design it on analog level. Additionally the circuit should be low power

12. ## Re: stretching the 0 pulse of a digital output with a certain T

Conceptually, how about you trigger the counter with the rising edge of your short pulse and let it count for as long as you need. When it is done counting, it generates a transition, say low to high, kind of ready signal. Then use a sort of a RS latch which is asserted low with the falling edge of your short pulse and deasserted to high with the counter ready signal.

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13. ## Re: stretching the 0 pulse of a digital output with a certain T

Hi,

In post#3 you talk about 50...100ms.
Why?
This is more than a million factor away...

Klaus

14. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by KlausST
Hi,

In post#3 you talk about 50...100ms.
Why?
This is more than a million factor away...

Klaus
I'm trying to do both variants, so i thought delaying it digitally would be easier.

Originally Posted by sutapanaki
Conceptually, how about you trigger the counter with the rising edge of your short pulse and let it count for as long as you need. When it is done counting, it generates a transition, say low to high, kind of ready signal. Then use a sort of a RS latch which is asserted low with the falling edge of your short pulse and deasserted to high with the counter ready signal.
I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for the "counter" which is a d-flipflop with its D connected to the Qn. The problem right now is that the counter will keep counting so i will have half the clock frequency on the output after the pulse goes high as in the simulation. does anyone has a hint how to make it stop after this clock cycle?

15. ## Re: stretching the 0 pulse of a digital output with a certain T

A counter by itself is a state machine. A counter the way you have done it will keep on counting for as long as there is clock. Surely you can design a counter that is triggered by your short pulse as you did but then when it reaches the count you need, it stops and waits for the trigger to start counting again.

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16. ## Re: stretching the 0 pulse of a digital output with a certain T

Yea that was my question if i can achieve that with some flipflops as it's an ic design so i can't use a ready ic

17. ## Re: stretching the 0 pulse of a digital output with a certain T

Yes, of course you can achieve it. Make the flow diagram of the thing and based on it design the circuit.
Here is a dirtier way of perhaps doing it. I did not simulate the circuit, so there is some possibility of error, but I hope you'll get the idea. I have assumed your short pulse is in sync with the clock as you show in your diagrams.

18. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by iaf
Hello, i have a digital output with varying pulse sizes and i want to stretch the 0 output for a constant T+ 0 pulse time. I have tried using a monostable multivibrator with a NAND gate but the problem i got is that the length of the pulse remains constant, which could be a problem if the pulse width is greater than the multivibrator output so how to add this time constant to the original pulse width instead?

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here's an image of the desired output
Trigger from the negative edge, and hold till positive edge. Retrigger again at positive edge.
Thats the logic. Just have to implement it.

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Childish problem. Whats the big concern ?

19. ## Re: stretching the 0 pulse of a digital output with a certain T

Originally Posted by sutapanaki
Yes, of course you can achieve it. Make the flow diagram of the thing and based on it design the circuit.
Here is a dirtier way of perhaps doing it. I did not simulate the circuit, so there is some possibility of error, but I hope you'll get the idea. I have assumed your short pulse is in sync with the clock as you show in your diagrams.

well thanks for your answer i could achieve it with only 2 flipflops with the reset pulse connected to the reset pin and it just does the required. Thanks for your effort though
Originally Posted by kripacharya
Trigger from the negative edge, and hold till positive edge. Retrigger again at positive edge.
Thats the logic. Just have to implement it.

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Childish problem. Whats the big concern ?
yea actually the problem was stopping in the "retriggering" after 2 clocks

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