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  1. #1
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    Error loop must terminate within 10,000 iterations (vhdl)

    Can someone help me solve this problem?

    I try to compile this code on quartus andd everytime appear this erro:

    Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations
    Its my code below:

    Code VHDL - [expand]
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    library ieee;
    library std;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use std.textio.all;
     
    --
    entity InstructionMemory is
        port (
            clk, rst : in std_logic;
            address : in std_logic_vector(31 downto 0);
            instr_out : out std_logic_vector(31 downto 0)
        );
    end entity;
    architecture aim of InstructionMemory is
     
        type instr_mem is array(0 to 20) of std_logic_vector(31 downto 0);
        signal imem : instr_mem := (others => (others => '0'));
     
    begin
        process (clk)
            file file_pointer : text;
            variable line_content : string (1 to 32);
            variable line_num : line;
            variable i : integer := 0;
            variable j : integer := 0;
            variable char : character := '0';
        begin
     
            file_open(file_pointer, "C:/Users/MM/Desktop/PF3/MIPS-Monocycle-32-bits-master/Testcases/instructions.txt", READ_MODE);
            while not endfile (file_pointer) loop -- this is line 31
                readline(file_pointer, line_num);
                READ(line_num, line_content);
     
                for j in 1 to 32 loop
                    char := line_content(j);
                    if (char = '0') then
                        imem(i)(32 - j) <= '0';
                    else
                        imem(i)(32 - j) <= '1';
                    end if;
                end loop;
                i := i + 1;
            end loop;
            file_close(file_pointer); -- Close the file
            wait;
        end process;
     
        process (clk, rst)
        begin
            if rst = '1' then
                instr_out <= "00000000000000000000000000000000";
            elsif clk'EVENT and clk = '0' then
     
                    assert (( (to_integer(unsigned(address)) mod 4194304)/4) < instr_mem'LENGTH)
                    report  "Simulation has ended"
                    severity ERROR;
                instr_out <= imem((to_integer(unsigned(address)) mod 4194304)/4);
            end if;
        end process;
    end architecture;

    This is the line 31:
    Code:
    while not endfile (file_pointer) loop -- this is line 31
    I dont know if the path of the instruction is wrong.

    this is the size of intructions, 22 lines.

    00000000111100000000100010010011
    00000001010000000000100100010011
    00000000101000000000100110010011
    00000000010100000000101000010011
    00000000001000000000101010010011
    00010000000000000000111010010111
    11111110110011101000111010010011
    00000000000010101010111000110011
    00000010000011100001110001100011
    00000000010010101010111000010011
    00000010000011100000100001100011
    00000000001011100001001100010011
    00000001110100110000001100110011
    00000000000000110010001010000011
    00000000000000101000000001100111
    00000001010010011000010000110011
    00000001100000000000000001101111
    00000001001001001000010000110011
    00000001000000000000000001101111
    01000001001001001000010000110011
    00000000100000000000000001101111
    01000001010010011000010000110011

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  2. #2
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    Re: Error loop must terminate within 10,000 iterations (vhdl)

    You are trying to synthesize a test bench in Quartus, this makes no sense. What do you want to achieve?



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  3. #3
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    Re: Error loop must terminate within 10,000 iterations (vhdl)

    I think it wasn't intended to be a simulation testbench. To load a rom from a file in vhdl, I think you can use an impure function to initialize the memory in the declaration section. see https://www.intel.com/content/dam/ww...qts_qii5v1.pdf 12-26 for info. also note that non-power-of-two depths might not be supported in all synthesis tools or may not infer optimal resources.



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  4. #4
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    Re: Error loop must terminate within 10,000 iterations (vhdl)

    We can surely discuss how to write synthesizable memory initialization. But this is pure test bench code.



  5. #5
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    Re: Error loop must terminate within 10,000 iterations (vhdl)

    how so? It is almost copied from examples in vivado's synthesis guide.

    --edit, it looks like altera/intel don't support textio for initialization while xilinx does. or at least as of two years ago. https://forums.intel.com/s/question/...language=en_US . The use of textio for init'ing roms is how some tools get around the lack of readmem in VHDL.
    Last edited by vGoodtimes; Yesterday at 08:28.



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  6. #6
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    Re: Error loop must terminate within 10,000 iterations (vhdl)

    No, Altera/Intel doesn't support textio for memory initialization. But that's not my point. The typical VHDL test bench code starts with a non synthesizable infinite loop and stops with "Simulation has ended".



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