pulse width stretching

1. pulse width stretching

i want to design a circuit for stretching the "0" output of my signal. I have seen the Monostable multivibrator but it stretches the "1" output. is there anyway flipping it or another topology for realizing that?

2. Re: pulse width stretching

Could you give us more information? Is this a digital system? Is there a clock? You could use a schmitt-trigger AND gate where the signal goes directly to one input and through an RC to the other input.

"Is there anyway of flipping it?" Of course; use an inverter.

3. Re: pulse width stretching

In addition, most monostable chips have trigger inputs for both polarities. Pulse stretching refers to retriggerable monoflop, otherwise the pulse width would be also limited.

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4. Re: pulse width stretching

Originally Posted by barry
Could you give us more information? Is this a digital system? Is there a clock? You could use a schmitt-trigger AND gate where the signal goes directly to one input and through an RC to the other input.

"Is there anyway of flipping it?" Of course; use an inverter.
it's a digital output of a d-flipflop which is clocked by a 50MHz clock. Adding an inverter will invert the "1" to "0" which is not the goal.

5. Re: pulse width stretching

Adding an inverter will invert the "1" to "0" which is not the goal.
barry answered your question in post #1 (how can we use a monoflop with inverse input polarity), you apparently forgot your question.

6. Re: pulse width stretching

Originally Posted by FvM
In addition, most monostable chips have trigger inputs for both polarities. Pulse stretching refers to retriggerable monoflop, otherwise the pulse width would be also limited.
I#m designing the circuit so i don't have a ready to use multivibrator

7. Re: pulse width stretching

I#m designing the circuit so i don't have a ready to use multivibrator
Fine, than just design it with correct polarity and don't forget the retrigger point if you expect input pulses longer than the monoflop period.

8. Re: pulse width stretching

Originally Posted by barry
Could you give us more information? Is this a digital system? Is there a clock? You could use a schmitt-trigger AND gate where the signal goes directly to one input and through an RC to the other input.

"Is there anyway of flipping it?" Of course; use an inverter.
sorry didn't get it. am i supposed to have two inputs?

9. Re: pulse width stretching

Originally Posted by iaf
sorry didn't get it. am i supposed to have two inputs?
I don't think there are any one-input AND gates.

10. Re: pulse width stretching

Originally Posted by FvM
Fine, than just design it with correct polarity and don't forget the retrigger point if you expect input pulses longer than the monoflop period.
how do i change the polarity? i just want to extend the 0 output for some ms as an example. The design i used was a NOR gate connected to a capacitor and resister with an inverter in the end giving the output

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11. Re: pulse width stretching

Low Going Pulse Stretcher using two NAND Gates ...
NAND_GATE
scroll down for schematic
Use "High Speed" and right hand device, best if, "Schmidt Trigger" Input
Width of trigger pulse must be wider than gate delays

Or use something like 74AHC123A or 74AHCT123A Monostable ...
MONO-STABLE
Has both Rising Edge & Falling Edge Triggers

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Can your Low-Going Pulse discharge a small Capacitor ?

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12. Re: pulse width stretching

Bad idea. Use this:

Have to consider pulse width, etc. in selecting RC. Can also put diode across R for narrow input pulse.

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13. Re: pulse width stretching

Originally Posted by barry
Bad idea. Use this:

Have to consider pulse width, etc. in selecting RC. Can also put diode across R for narrow input pulse.
why is it bad idea?
is there any schematic of this schmitt trigger? as i have to design it in that case

14. Re: pulse width stretching

Originally Posted by iaf
it's a digital output of a d-flipflop which is clocked by a 50MHz clock. Adding an inverter will invert the "1" to "0" which is not the goal.
Would I be wrong in assuming that you are on the scope of a programmable logic circuit design? In this case, it would make little sense to implement this circuit with an analog approach.

15. Re: pulse width stretching

Originally Posted by andre_teprom
Would I be wrong in assuming that you are on the scope of a programmable logic circuit design? In this case, it would make little sense to implement this circuit with an analog approach.
no it's actually an analog design just having a digital output

16. Re: pulse width stretching

Originally Posted by iaf
why is it bad idea?
is there any schematic of this schmitt trigger? as i have to design it in that case
It's a bad idea because you'll never pull the input lower than one diode drop+Vlo of the source. This may not be low enough to effect a logic '0'.
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17. Re: pulse width stretching

so how would i design this schmitt trigger with 2 inputs?

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another problem with this design is that the pulse will be stretched in a constant time regardless how long the input takes, which is applicable in case if the input is longer the RC time constant, so is there a solution to add this time constant to the original width?

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18. Re: pulse width stretching

is there any schematic of this schmitt trigger? as i have to design it in that case
Two single ST gates and an AND.

19. Re: pulse width stretching

Originally Posted by FvM
Two single ST gates and an AND.
What'S an ST gate?

20. Re: pulse width stretching

ST= Schmitt Trigger.

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