Hello, everyone

I'm a master student from National Taiwan University ,and engaged in the research of diagnosis.

I have trouble when I tried to verify my thesis with leon3mp, which is a benchmark circuit.
First, I generated transition delay fault pattern set using the commercial tool.

Then, I use the fault simulation tool, which is implemented by our lab, to generate faillog. Faillog contains all the failing output together with its expected value and got value.

And then, I put the faillog to our diagnosis tool and commercial tool for the purpose of comparing our tool with commercial tool.
I get error messages that the expected output value in faillog mismatch with simulation of commercial tool.

For example, if faillog says one failing output's expected value is 1, the expected value of this output generated by commercial tool is 0.

One possible reason is our fault simulation tool have some bug, but other benchmarks don't raise this mismatch problem.

Is there any suggest to this problem? Or is someone has experience to use leon3mp? please contact me, thanks a lot.