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    Delay a signal in a system verilog testbench using jaspergold

    Hello everyone,

    I am an electrical engineer student and now I'm in an internship. I'm working with jaspergold and I need to delay a signal for a portion of the clock cycle (half cycle or less or more) but I am blocked .
    Here is one of the ways I tried :

    assign #0.5 ack_d = ack

    I also tried :

    always @(posedge clk) ack_d <= #0.5 ack;

    I used also #2 and #3 but always it is delayed by only one cycle.

    Can anyone help me please?

    Thank you in advance.
    Last edited by BradtheRad; 11th June 2019 at 01:47. Reason: made keywords boldface

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  2. #2
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    Re: Delay a signal in a system verilog testbench using jaspergold

    first things first... delay statements are not synthesizable and are rarely used. make sure you understand what is being asked of you. it is ok in a testbench, never in a design.

    second, you have a non-blocking assignment inside an always block, it is triggered by the clock. it doesn't matter if ack signal changes, it is only assessed at the clock edge.

    finally, why can't you use the negedge of the clock instead of fiddling with delays?
    Really, I am not Sam.


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  3. #3
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    Re: Delay a signal in a system verilog testbench using jaspergold

    Thank you for your answer.
    I'm adding the delay at the testbench and not the design.
    I tried working with negedge and i added "clock -both_edges clk" in the TCL file but the assertion is failing because its evaluated at both edges two.



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    Re: Delay a signal in a system verilog testbench using jaspergold

    the number after a # delay (i.e. in your case assign #0.5 ack_d = ack) means #(timeunit) if your testbench has a directive `timescale 1ns/1ps or a timeunit 1ns statement then your # delay should be an integer in those units.

    SV allows you to specify the units in a # delay statement.
    So if you have timeunit 1ps and timeprecission 1ps and your clock is 400 MHz then you have a clock period of 2.5 ns and to have a delay of half of that you use one of the following:
    Code Verilog - [expand]
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    #1250; // this is 1250 timeunits i.e. 1250 ps or 1.25 ns
    // or
    #1.25ns; // explicitly says 1.25 ns, if timeunit is 100ps then the result would be #1.2 (I believe it truncates)
    // or
    #1250ps; // explicitly set 1250 ps of delay (i.e. 1.25 ns)
    The delay is an integer, which is why regardless of the timeunits used in your testbench #0.5 ends up as a #0 statement as you didn't specify say #05ns for a half nanosecond delay.


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  5. #5
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    Re: Delay a signal in a system verilog testbench using jaspergold

    Quote Originally Posted by haammzzaa View Post
    Thank you for your answer.
    I'm adding the delay at the testbench and not the design.
    I tried working with negedge and i added "clock -both_edges clk" in the TCL file but the assertion is failing because its evaluated at both edges two.
    fix your assertion then.
    Really, I am not Sam.



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