Wyre
Newbie
When we define the clock uncertainty values for a design ( assume in this case, we are designing a block/partition of a chip), we usually talk about them in percentages i.e. 8% and 4% of the clock period for Setup and Hold uncertainty resp. If we break uncertainty down, its essentially:
Setup Uncertainty = Clock Jitter + Clock Skew + Margin
Hold Uncertainity = Clock Skew + Margin
Do the values of the parameters (except skew) above come from the top level designer or is there some sort of methodology to determine them?
On a side note: What exactly is Margin?
Thanks
Setup Uncertainty = Clock Jitter + Clock Skew + Margin
Hold Uncertainity = Clock Skew + Margin
Do the values of the parameters (except skew) above come from the top level designer or is there some sort of methodology to determine them?
On a side note: What exactly is Margin?
Thanks