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[SOLVED] Methodology to calculate the Clock Uncertainity values.

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Wyre

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When we define the clock uncertainty values for a design ( assume in this case, we are designing a block/partition of a chip), we usually talk about them in percentages i.e. 8% and 4% of the clock period for Setup and Hold uncertainty resp. If we break uncertainty down, its essentially:

Setup Uncertainty = Clock Jitter + Clock Skew + Margin
Hold Uncertainity = Clock Skew + Margin

Do the values of the parameters (except skew) above come from the top level designer or is there some sort of methodology to determine them?

On a side note: What exactly is Margin?


Thanks
 

When we define the clock uncertainty values for a design ( assume in this case, we are designing a block/partition of a chip), we usually talk about them in percentages i.e. 8% and 4% of the clock period for Setup and Hold uncertainty resp. If we break uncertainty down, its essentially:

Setup Uncertainty = Clock Jitter + Clock Skew + Margin
Hold Uncertainity = Clock Skew + Margin

Do the values of the parameters (except skew) above come from the top level designer or is there some sort of methodology to determine them?

On a side note: What exactly is Margin?


Thanks

someone will implement the top level clock tree and should be able to give you some estimates of how bad the clock distribution is. That is the skew. Margin is margin, extra timing that you put in there 'just in case'. Jitter is external to the chip or a property of the PLL. Someone should be able to tell you that from the specs.

All of that being said, there is a lot of confusion about what those words mean. It changes from tool to tool, company to company, designer to designer. Make sure you are talking about the same thing when you reach out to someone else.
 
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    Wyre

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