# [moved] Digital Transition Capture

1. ## [moved] Digital Transition Capture

Hi everyone,

I need a circuit is designed to detect whether there has been at least one transition during the past clock period. This image show detail the operating principle of the circuit. I am not specialized in digital, so i don't know this circuit is possible? Please give me some information about the circuit.

Thanks you!

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2. ## Re: Digital Transition Capture

Hi,

A simple FSM will do it.

You need two pipelined registers, reg1 and reg2. Keep the current data in reg1. On the next clock edge, move the content of reg1 to reg2. Always compare each bit in reg1 with corresponding bit in reg2 using XOR gate. You'll get a '1' when the contents are different. You'll get a '0' otherwise.

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OR the outputs from all the XOR gates.

3. ## Re: Digital Transition Capture

I wonder whether some kind of flip-flop detector would work. However I'm not certain whether you can get it to it work on a single up or down transition, or whether it requires an entire cycle.

From the opposite standpoint what does your output do? It stays high most of the time, and it drops when it sees no transition during a clock cycle. Therefore it might also be called a missing pulse detector. A 555 timer IC can be made to do that.

4. ## Re: Digital Transition Capture

Hi Akanimo,
This circuit work with clock frequency is smaller than the input signal frequency.
Therefore, I think it is impossible to use the your method.

Thanks for your help. The method use 555 timer IC is very suitable for my case. But I can't use the IC 555, I need a integrated circuit in my IC. Do you have any other method to design a missing pulse detector?
Thanks,

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5. ## Re: Digital Transition Capture

What are your frequencies? List them so we know. Even the 555 has limitation in frequency.

Is that the original clock or a derived clock?

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6. ## Re: Digital Transition Capture

The "at least one transition" point needs clarification. There can be potentially many transitions with high repetition frequency, under circumstances they may be detected as zero transitions.

7. ## Re: Digital Transition Capture

Hi,
We need to operate at the frequency greater than 10MHz. Is the IC 555 can work in this case? Is this depend on the technology?
I wonder if I use 65nm CMOS technology with the same topology of IC555, can I obtain the expected operation frequency?

Thanks,
Chau

8. ## Re: Digital Transition Capture

10MHz is too high for a 555. 3-MHz is specified for the cmos version.

BTW, when you say 10MHz, is it the clock frequency or the data. You didn't say which and you didn't mention the other.

9. ## Re: Digital Transition Capture

Originally Posted by Akanimo
10MHz is too high for a 555. 3-MHz is specified for the cmos version.

BTW, when you say 10MHz, is it the clock frequency or the data. You didn't say which and you didn't mention the other.
Let see the figure below. In which, the clock frequency is 30 MHz, the input data has 0's pulse width is 5ns.

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10. ## Re: Digital Transition Capture

Your latest waveform makes less sense than the post #1 waveform which changed the output on the rising clock edge.

Please specify the detection algorithm you want to implement unambiguously, e.g. as a state diagram.

11. ## Re: Digital Transition Capture

You have mentioned too many frequencies: 10MHz, 30MHz, and the "input" waveform of your last post shows a frequency that is about double that of the 30-MHz clock.

Anyways, the idea is that the clock is in tens of MHz.

I asked you earlier on how you got the clock signal, whether it is a primary clock or a generated clock but you didn't give any response in that regard.

What I think you can do right now is to use a clock multiplier (a PLL would be sufficient) to generate a fast enough clock signal from your 30-MHz clock so that you can use my approach of Post #2.

I noticed that your output logic level of Post #10 is reversed compared to that of Post #1. This means you would replace the XOR gate with an XNOR gate.

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But this means that the generated clock frequency has to be faster than 1/5ns ( =200MHz).

12. ## Re: [moved] Digital Transition Capture

Attached is a very "rough" idea for Latch & Hold

1) The Data Signal is converted from "H-to-L" & "L-to-H" transitions to very narrow Pulses - ( width needs verified )
2) One, or more, Data Pulses will SET the R-S Latch, asynchronously.
3) The rising edge of the Clock triggers the D-Latch to transfer the state of the R-S Latch to the OUTPUT Pin.
4) The rising edge of the Clock also RESETS the R-S Latch - ( I need to SYNC this with a new Data Transition Pulse )
5) The RESET of the R-S latch can be blocked by an active Transition of the Data Signal - ( currently very poorly )

The logic to handle a "simultaneous" Data Transition and a Rising Clock Edge RESET needs to fixed by making them always sequential.

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