+ Post New Thread
Results 1 to 12 of 12
  1. #1
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Active-HDL VHDL simulation problem

    Hi all,
    I am new to Active-HDL. I am starting to learn the tool by simulating a simple two input AND gate. The code is following,
    Code:
    --and.vhd
    entity and_gate is  
                port (A,B:in bit;C:out bit);
    end and_gate;
     
    architecture and_gate_ar of and_gate is
    begin               
       C<=A and B;
    end and_gate_ar;
    and the testbench is the following,
    Code:
    --and_tbench.vhd
    entity tb_en is
    end tb_en;
    
    architecture tb_ar of tb_en is
    
    component and_gate
    port(
    	A : in BIT;
    	B : in BIT;
    	C : out BIT
    );
    end component;
    
    signal a_i,b_i:bit;
    signal out_c:bit;
    
    begin
    stimulus: process
                  begin
                      a_i <= '0'; b_i <= '0';
                      wait for 100 ns;               
                      a_i <= '0'; b_i <= '1';
                      wait for 100 ns;
                      a_i <= '1'; b_i <= '0';
                      wait for 100 ns;
                      a_i <= '1'; b_i <= '1';
                      wait for 100 ns;
                      if now = 400 ns then
                          wait;
                      end if;
    end process stimulus; 
    
    add1 : and_gate port map(A => a_i, B => b_i, C => out_c);
    
    end tb_ar;
    but when i simulate the code i get no output for the signal out_c, i.e., no output,
    Click image for larger version. 

Name:	simulation.png 
Views:	8 
Size:	287.8 KB 
ID:	153546

    please help me where I am wrong ??
    I tried the same code in modelsim it is working OK, but why not active-hdl??
    I have to work in active-hdl only for my project.

    please help me, thanks in advance
    thanks

  2. #2
    Advanced Member level 5
    Points: 24,418, Level: 38
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,688
    Helped
    1036 / 1036
    Points
    24,418
    Level
    38

    Re: Active-HDL VHDL simulation problem

    I would suggest you expand your structure and look at the signals of the underlying elements, I.e., your actual gate.

    And you don’t have “no output”, you have a zero output; there’s a difference.



    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 4
    Points: 7,568, Level: 20
    Achievements:
    7 years registered

    Join Date
    Jul 2010
    Location
    Sweden
    Posts
    1,013
    Helped
    387 / 387
    Points
    7,568
    Level
    20

    Re: Active-HDL VHDL simulation problem

    Don't use signal type "bit". With "bit" you will lose a lot of the advantages with simulation. In this case you can't see if out_c is driven by something or not.
    One explanation for your problem is that the AND gate wasn't connected during elaboration.
    Replace "bit" with "std_logic" and show us the simulation result. If out_c isn't connected it will show as "U" (not assigned, the default value for std_logic).

    Edit:
    std_ulogic is also OK, it is better for detection of multiple drivers.
    Last edited by std_match; 9th June 2019 at 00:14.



    •   AltAdvertisement

        
       

  4. #4
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Re: Active-HDL VHDL simulation problem

    Thanks for fruitful replies, I used "std_logic" as std_match suggested but still no luck,
    this is the updated and.vhd with "std_logic",

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    entity and_gate is
    port (A,B:in std_logic;C:out std_logic);
    end and_gate;

    architecture and_gate_ar of and_gate is
    begin
    C<=A and B;
    end and_gate_ar;
    this is the updated testbench and_tbench.vhd with "std_logic",

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    entity tb_en is
    end tb_en;

    architecture tb_ar of tb_en is

    component and_gate
    port(
    A : in std_logic;
    B : in std_logic;
    C : out std_logic
    );
    end component;

    signal a_i,b_i:std_logic;
    signal out_c:std_logic;

    begin
    stimulus: process
    begin
    a_i<='0';b_i<='0';
    wait for 100 ns;
    a_i<='0';b_i<='1';
    wait for 100 ns;
    a_i<='1';b_i<='0';
    wait for 100 ns;
    a_i<='1';b_i<='1';
    wait for 100 ns;
    if now=400 ns then
    wait;
    end if;
    end process stimulus;

    add1 : and_gate port map(A=>a_i,B=>b_i,C=>out_c);

    end tb_ar;
    and the output
    Click image for larger version. 

Name:	simulation.png 
Views:	8 
Size:	304.5 KB 
ID:	153576

    you were right, If out_c isn't connected it will show as "U" (not assigned, the default value for std_logic).

    please help me
    thanks a lot



  5. #5
    Advanced Member level 5
    Points: 24,418, Level: 38
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,688
    Helped
    1036 / 1036
    Points
    24,418
    Level
    38

    Re: Active-HDL VHDL simulation problem

    What about a_i and b_i? If they’re unconnected c_out will be undefined. Show ALL your signals. There’s probably a problem with your elaboration



    •   AltAdvertisement

        
       

  6. #6
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Re: Active-HDL VHDL simulation problem

    Thanks sir but i am new to Active-HDL please tell me how to show ALL my signals, but please consider the following screen shot,
    Click image for larger version. 

Name:	simulation.png 
Views:	7 
Size:	318.2 KB 
ID:	153577

    please help me
    thanks



  7. #7
    Advanced Member level 2
    Points: 2,970, Level: 12

    Join Date
    Aug 2016
    Posts
    518
    Helped
    88 / 88
    Points
    2,970
    Level
    12

    Re: Active-HDL VHDL simulation problem

    Hi,

    I'd suggest that you take add1 above stimulus in your testbench and then try again.
    -------------
    --Akanimo.



  8. #8
    Advanced Member level 4
    Points: 7,568, Level: 20
    Achievements:
    7 years registered

    Join Date
    Jul 2010
    Location
    Sweden
    Posts
    1,013
    Helped
    387 / 387
    Points
    7,568
    Level
    20

    Re: Active-HDL VHDL simulation problem

    The hierachy looks wrong. The and gate "add1" should be a subcircuit to "tb_en". Only the stimuli process is listed, so the and gate has not been connected.
    Run it again in modelsim and look at the hierarchy.

    If you remove the component declaration, you will get an error message if the and gate isn't connected. That would be an advantage here.
    What you have now is a "black box" that isn't connected. Black boxes need a component declaration, but that is only causing confusion now.

    If you remove the component declaration, you only have to add the keyword "entity" to the instantiation:
    Code:
    add1 : entity and_gate port map(A=>a_i,B=>b_i,C=>out_c);
    Edit:
    I think the problem is that the and gate isn't in the "work" library, and all libraries except work must be specified.
    Last edited by std_match; 9th June 2019 at 11:42.



  9. #9
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Re: Active-HDL VHDL simulation problem

    thanks to all I took add1 above stimulus in my testbench as Akanimo suggested, I also removed the component declaration and used
    add1 : entity and_gate port map(A=>a_i,B=>b_i,C=>out_c);
    , even I made my design and library name as 'work'

    but still no luck
    I don't know what to do??
    please help me



  10. #10
    Super Moderator
    Points: 31,820, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,365
    Helped
    1726 / 1726
    Points
    31,820
    Level
    43

    Re: Active-HDL VHDL simulation problem

    I would delete any work or other libraries that you've compiled your code into, then recompile the design into a work library and run your simulation again.

    I would suspect you have an old version of a file that is compiled and it's being used and the updated file is compiled to a different library so you don't see any elaboration errors.

    This is why I always script the compile and run flow for simulation (and the first line of my script has a check for library-delete library and create a new empty one)



    •   AltAdvertisement

        
       

  11. #11
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Re: Active-HDL VHDL simulation problem

    Hi I tried to compile the testbench in a different library as ads-ee suggested (actually I think I could not understand fully what ads-ee said) but still no luck --- same output as before,

    Pls somebody give me a short video tutorial how to do ?

    Please help me
    thanks and regards



  12. #12
    Newbie level 5
    Points: 812, Level: 6

    Join Date
    Apr 2015
    Posts
    9
    Helped
    0 / 0
    Points
    812
    Level
    6

    Re: Active-HDL VHDL simulation problem

    The same thing is happening with Riviera Pro also
    Please help me
    Thanks



--[[ ]]--