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    I2c Master - Can't receive ack from slave

    http://pastiebin.com/embed/5cfb27b5a120a <-- Master

    https://imgur.com/aZ76pCF <--- Block Diagram

    https://imgur.com/8nqwfJh <-- Pin editor

    https://imgur.com/bHPApTf <-- Simulation

    Right now I have a master that was based off of Pedroni's i2c generic master from Finite State Machines, originally I had SDA <= 'Z' in the states I needed and then assigned SDA <= '1' or '0' for commands/addresses. This did not work unfortunately. So I did some reading and read that to incorporate a proper open drain I should do SDA <= '0' when <condition> else 'Z'. So I did this instead; still nothing. Then I tried to do a weak pull-up resistor too, but to no avail, it still did not work. I am trying to interact with a RGB TCS34725 color sensor. End goal is to power a small car, and try and keep it inside the lines. One thing I am noticing is when I use the wrong address I do not even get a error ack back, the ack is always '0'. So I think it has to do with the i2c bus, and not the code because if I am not interpreting the simulation wrong, the SCL and SDA should match I2C protocols/standards. All I am trying to do is read the device ID, once I know I can do that, building the UI will come easily. I appreciate any help that is offered, thank you for your time.


    EDIT: Realized I did not set the pull-up resistor to the block diagram. I am now getting a no ack now from Slave, but now I can't get it to send a '0' when I send the correct slave address.
    Last edited by chrisistoocool; 8th June 2019 at 05:06.

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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Go into details about the pull-up resistor strength and any level-shifting ic's between the devices. Also, does the design work at lower i2c clock rates. eg, 1/10th or 1/100th the normal rate.

    I strongly prefer oversampling based i2c controllers vs ones that try to use scl directly as a clock. This might not be an issue in this case, but it's not really a fpga targeted design.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    I would like to say it is in the range of 28-47 if I am reading the cyclone 4 data sheet correctly since I will be using 3V. Also it doesn't seem like there are any color sensors just for FPGA, just color sensors that support I2C. I can try oversampling, and just create probes for rising/falling edge of i2c but the FPGA should be able to implement a steady SCL clock. I checked the sensor out on an Arduino, and everything works. My master works with a slave I made, which leads me to the conclusion the FSM works. Which is weird sense I know the sensor works, and I know my master works, I am stuck on why I can't get a simple ack back from the slave using the slave address. If you know of some FPGA color sensors, I would gladly switch to them instead.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Not clear if you are describing a simulation or hardware operation problem.

    In functional simulation, you need to add a 'H' weak pullup to your test bench. In real hardware, an external 1 - 5k resistor is required.


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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Reviewing your documents, I see that you have enabled FPGA internal pullup. It's probably too weak for hardware operation and it's not modelled in functional simulation. Thus SDA isn't pulled high.


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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Most FPGA's internal pullups are on the order of 50K-150K ohms and are there specifically to ensure the input buffers see a valid logic level instead of a floating pin. They are definitely not to be used as a replacement for board level pull up resistors.


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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Just to make sure I understand, I should try to hook it up to an external open drain circuit or do I just need to attach a resistor? I am assuming I will need to actually make an open drain circuit because the pull-up should be in-between the power and the master/slaves, but just asking to save time. Then try and find the RC time for the SDA to make sure it meets the time constraints of the speed I will be running the clock. Thankfully the sensor only uses the SDA as an open drain, so I should be able to keep clock as it is.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    You seem to make simple things complicated. Open drain function can be performed by the FPGA if the I2C bus voltage is 3.3V (or lower), you are doing it correctly by switching the output between '0' and 'Z'. You need an external pullup resistor to 3.3V. 1 kohm is expected to work without calculation, lower values are probably not supported by the I2C peripherals. You need to take care that the peripherals can work with 3.3V bus voltage. If they require 5V, a level converter would be necessary.

    Your initial post describes a simulation problem, it must be handled in simulation.


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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Thank you for your reply, I will try your suggestions this weekend. The sensor can operate at 3.3V, I made sure to check for that specifically. I did not mean to make it sound like a simulation problem, I only posted the simulation to show that the master was meeting SDA/SCL time requirements. Everything mentioned in my post involves actual testing. I have a slave that I can write to and read from, I confirm this by writing the 8 bits to 8 LEDS, and I get ack and no ack depending if I send the correct address or not. So I know my master works in this sense at least. At the moment, I can't get an Ack, '0', back from the RGB slave when I first send the slave address, I am only getting no acks , '1'. I am assuming this is because I am not using the correct pull-up resistor and the RGB slave can't pull it down to a logic 0 for the FPGA to read. Hopefully what you said will fix that! Thank you again for your time!!



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    I did not mean to make it sound like a simulation problem, I only posted the simulation to show that the master was meeting SDA/SCL time requirements. Everything mentioned in my post involves actual testing.
    Thanks for clarifying but how can we know? If you show real measurements, there should be an oscilloscope waveform. As far as I understand you don't know how the SDA actually looks like.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    I do not have an oscilloscope unfortunately, but I am using a slave that I made to test the functionality of the the master. The SDA must go high or low for the master to be communicating with the homemade slave, because the LEDs change by writing to the slave then reading from it. I could be wrong though.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    you can try lowering the i2c clock rate. For testing, using something like 1khz-10khz might be fine.



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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Hi,

    I recommend to treat SDA and SCL equally, "0" and "Z" only.

    In doubt refer to I2C specifications.

    Klaus
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  14. #14
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    Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    I recommend to treat SDA and SCL equally, "0" and "Z" only.

    In doubt refer to I2C specifications.
    No problem to use push-pull driver for SCL in single master system if the slaves don't perform clock stretching. Most simple devices don't and have input only SCL pin.



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