Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

devideing large MOSFET gate using muti fingers

Status
Not open for further replies.

Junus2012

Advanced Member level 5
Joined
Jan 9, 2012
Messages
1,552
Helped
47
Reputation
98
Reaction score
53
Trophy points
1,328
Location
Italy
Activity points
15,235
Dear friends,

it is usually preferable to divide large MOSFET to some number of gate fingers to reduce the channel resistance, also there is other advantages when we use even number of gate fingers to reduce the drain area and hence improve the AC characteristics. However in analog circuit design I believe that there must be a price of this operation.

Therefore I would like to ask you please about the side effects of dividing the transistor using large number of fingers, what is the maximum division I should do ?

Thank you very much
 

Two things that immediately come to mind are that you don’t want to make the devices so small that matching suffers. You also don’t want to make them so small that you can’t contact enough metal on the stripes to meet electromigration requirements.
 
Dear ljp

thank you for your reply,

if I am using channel length of 1 um. and I go down to 0.5 um/1 um, is this considered small ?

thank you
 

That depends on what process node you’re working in. What is the minimum feature size in the process you’re working in? Also, your pdk will have a section on matching. That should provide additional guidance regarding how small is acceptable for your application.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top